Symptom: DMA reads stale data after CPU wrote the buffer. CPU cache is hardware-coherent. Buffer is in shareable memory.
Verify CPU wrote the buffer before DMA start — check program order.
Check the platform's ordering requirement between descriptor publication and the DMA doorbell; do not select a barrier instruction without the architecture and driver contract.
Verify DMA uses coherent path (not bypassing coherency).
If the path is non-coherent, verify the platform DMA mapping/synchronisation calls for the transfer direction and ownership transition rather than inserting a raw cache instruction by default.
Check whether the buffer shares a maintenance granule with unrelated dirty data; partial-granule ownership can require bounce buffering, alignment or platform-specific handling.
Assuming hardware coherency eliminates all flush/invalidate needs.
DMA through non-coherent path to 'coherent' memory.
Missing or incorrect publication/completion step between CPU data/descriptor updates and the device notification.