In a common non-inverted UART format, idle is high and a low start bit is followed by configured data bits, optional parity and a high stop interval. Many UARTs send the least-significant data bit first, but framing options and polarity are implementation/configuration contracts.
A receiver qualifies the start bit and samples according to its own clocking algorithm; oversampling by 16 is common but not universal. Allowable transmitter/receiver baud mismatch depends on sample placement, frame length, resynchronisation behaviour, jitter and both clock errors, so use the controller/device specification rather than a universal ±3% rule.
Baud = clock / divisor — integer divisor limits available rates.
FIFO depth determines how long the CPU can ignore the UART.
Overrun: an arriving character cannot be retained because the receiver holding register/FIFO has no available capacity under that implementation's policy.
Hardware flow control commonly uses RTS/CTS, but signal direction, polarity and automatic FIFO-threshold behaviour depend on DTE/DCE wiring and the UART implementation. Confirm what the local controller calls RTS and when the remote transmitter must stop; account for bytes already in flight.
Software flow control reserves control characters such as XON/XOFF in the byte stream. Arbitrary binary payload needs an agreed escaping/framing rule or software flow control disabled; it is not inherently impossible, but raw unescaped bytes can be misinterpreted.
Size receive service from FIFO capacity, trigger level, worst-case service latency, frame bits per character and bytes already in flight.
DMA on UART: watch for underrun on TX (DMA too slow).
Console UART in boot: polling mode avoids interrupt setup complexity.
Baud = clock / divisor — integer divisor limits available rates.
FIFO depth determines how long the CPU can ignore the UART.
Overrun: an arriving character cannot be retained because the receiver holding register/FIFO has no available capacity under that implementation's policy.