Primary debug scenario

Symptom: UART console garbled at 115200 baud. Works at 9600. No flow control.

Triage steps

1. Verify baud divisor: actual baud vs target (check clock source).

2. Measure each endpoint's actual bit period and compare the accumulated sampling error with the receiver's documented tolerance for this frame format.

3. Check if clock source changed (PLL reprogramming affects UART clock).

4. At high baud: ISR latency may cause overrun — check FIFO status.

5. Scope TX/RX: clean edges? Noise on the line?

Common pitfalls

• Blaming external device when baud rate is wrong.

• FIFO too shallow for ISR latency at high baud.

• Ignoring clock source when baud suddenly breaks.