Boot fail → training transcript. Runtime ECC → margin check + address analysis. Bandwidth regression → scheduler profile + firmware diff. Data corruption → address map + coherency check.
Memory bugs are rarely in one layer. A 'PHY failure' may be caused by controller issuing illegal commands. A 'software bug' may be wrong memory attributes causing cache incoherency.
Always collect: training log, mode registers, ECC counters, traffic replay.
Temperature correlation: compare margin measurements and error rates at controlled conditions; correlation does not identify the failing layer on its own.
Multi-channel: localise the affected channels, ranks, banks, lanes and addresses before ranking SI, power, device, controller, firmware and mapping hypotheses.
Always collect: training log, mode registers, ECC counters, traffic replay.
Temperature correlation: compare margin measurements and error rates at controlled conditions; correlation does not identify the failing layer on its own.
Multi-channel: localise the affected channels, ranks, banks, lanes and addresses before ranking SI, power, device, controller, firmware and mapping hypotheses.