Symptom: ECC correctable error rate climbing over 3 months in field. No uncorrectable errors yet. Same firmware revision.
Correlate ECC addresses — always same region? Same bank?
Compare training margins at failure time vs factory baseline.
Check temperature log — margin narrows at high temp?
For dispersed addresses, compare syndrome bits, lanes, channels, rails and time correlation; SI degradation and voltage droop are candidates, not conclusions.
For clustered addresses, translate the addresses through the real channel/rank/bank/row map and check allocation history; a hot software buffer, a physical region, one device or one lane can each create a cluster.
Ignoring correctable ECC trend until uncorrectable happens.
Replacing DRAM chips when SI/margin is the root cause.
Debugging data without checking memory attributes and coherency.