For DDR3/DDR4, write levelling compensates for the different arrival times of CK and write DQS at a DRAM device. During this training mode, the controller adjusts DQS phase relative to CK and uses feedback from the DRAM on DQ. The objective is the required DQS-to-CK timing relationship, not centring write data in a DQS sampling window. See the DDR3/DDR4 write-levelling explanation in AMD PG150.
DQ-to-DQS deskew and centring are separate data-timing tasks. Read training sets up capture of data returned with DQS; voltage-reference calibration concerns a voltage threshold rather than a clock phase. Names and algorithms vary by PHY, so record the relationship each reported result measures. A pass flag is not a quantified eye margin: retain the available timing/voltage margins and validate the required operating corners.
TRAINING RELATIONSHIPS (DDR3/DDR4 teaching map)
Write levelling: controller DQS -> DRAM CK relationship
DRAM DQ -> training feedback
Write data timing: DQ -> DQS capture relationship at DRAM
Read data timing: returned DQ/DQS -> PHY capture setup
What to notice: DQ feedback during write levelling is not
the same task as adjusting normal write-data sampling margin.
Question: does a write-levelling pass prove DQ is centred?
Answer: no; inspect the separate data-timing calibration.DRAM speed bins (DDR4-3200, LPDDR5-6400) define timing parameters: tRCD, tRP, tRAS, tRFC. Mode registers (MRWs) configure the DRAM chip. Firmware must match MRW settings to the speed bin and board design.
Gear-down mode, DLL-off operation and low-power modes can change timing or re-entry requirements. Follow the selected memory, controller and PHY specifications for any required reconfiguration, training or settling sequence; do not assume every mode transition has the same rule.
Mode register dump is the first artifact in any memory bring-up debug.
Training firmware is part of the protocol contract — version it.
Board skew and package routing affect margins as much as silicon.
Mode register dump is the first artifact in any memory bring-up debug.
Training firmware is part of the protocol contract — version it.
Board skew and package routing affect margins as much as silicon.