Start with link history, negotiated capability and error counters. Then correlate credits, request identity, routing, completions and software setup for the failing operation. These observations narrow hypotheses: L0 does not certify every transaction, and a timeout does not by itself identify a defective endpoint. Check reset, enable bits, mappings and permissions as well as the physical path.
Each layer has distinct evidence. LTSSM trace for physical. Credit counters for data link. TLP log for transaction. Config space dump for enumeration.
PCIe DEBUG EVIDENCE (hypotheses, not verdicts)
link history / configured limits / margin / error counters
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request type / requester+tag / route / completion status
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BAR access OR device DMA mapping / enable bits / ownership
Correlate one failing operation across all three views.
A healthy link state alone does not clear the data path.Draw the diagram before reading waveforms.
Name the transaction ID on every debug step.