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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals25
  • AMBA Family (APB / AHB / AXI)17
  • Coherence Fabrics (ACE / CHI)17
  • Memory Interfaces (DDR / LPDDR / HBM)17
  • PCIe & CXL17
    • PCIe Layering & TLPs
    • Enumeration & Link Training
    • CXL Attach Modes
    • PCIe / CXL Debug
      • PCIe / CXL Debug: Concepts
      • PCIe / CXL Debug: Integration
      • PCIe / CXL Debug: Debug
      • PCIe / CXL Debug: Interview
    • PCIe & CXL: Tricky Q&A
  • Embedded Peripherals (I2C / SPI / UART)17
  • High-Speed I/O (USB / Ethernet / MIPI)17
  • Protocol Verification & Compliance17
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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←PCIe / CXL Debug
  1. Topics
  2. Bus Protocols
  3. PCIe & CXL
  4. PCIe / CXL Debug
  5. PCIe / CXL Debug: Debug
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    Interface ProtocolsAll levels

    PCIe / CXL Debug: Debug

    Debug for PCIe / CXL Debug.

    Primary debug scenario

    Symptom: Device enumerates but DMA timeout. Link x4 Gen4 healthy. AER shows no errors. Driver times out on read.

    Triage steps

    1. Check completion credits at root port and endpoint.

    2. TLP trace: are MemRd TLPs sent? Are CplD TLPs returned?

    3. Distinguish CPU access to endpoint BAR registers from device DMA to host memory. For host-directed DMA, check the DMA address returned by the platform mapping API, its lifetime, direction and any IOMMU translation/permission; it need not point inside the endpoint BAR.

    4. Check bus-master enable and the actual request size against configured MPS/MRRS, buffer limits and path capabilities; do not require all fields to have identical values at every function.

    5. If CXL: separate .io config from .cache/.mem data path.

    Common pitfalls

    • Debugging driver before confirming TLP completion.

    • Ignoring AER correctable error trend.

    • Confusing enumeration success with data path health.

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    See also

    • PCIe / CXL Debug: Concepts