Symptom: A read returns correct data in block simulation but stale data on silicon. Block-level VIP passes. Full-system test fails intermittently under multi-core load.
Leading hypotheses: Leading hypotheses include attribute/coherency mismatch, address translation, bridge mapping, reset/power state, response association and integrity or timing faults. The intermittent multi-core condition raises concurrency-sensitive hypotheses but does not eliminate the read channel or physical path.
Tag failing read: ID, address, cache line, timestamp, initiating master.
Dump page table / memory attributes for that address — cacheable? shareable?
Trace physical path through interconnect — list every bridge and attribute transform.
Compare VIP txn log at master side vs slave side of each bridge.
Run 2-txn litmus: CPU write same line, DMA read same line — reproduce?
If coherent system: check snoop participation for that address range.
Reduce to smallest master pair that reproduces stale read.
Debugging data values without checking transaction attributes.
Assuming block VIP path equals chip path.
Blaming slave when bridge changed the contract.
Fixing with cache flush in software without understanding why coherency failed.
Symptom: Simulation and silicon both pass directed tests. Fails only when GPU and CPU access same buffer concurrently.
Map buffer address to shareability domain.
Verify GPU path participates in coherency (snoop or explicit flush).
Profile: are CPU and GPU using different cache lines or false-sharing one line?
Run the architecture/platform-defined producer-consumer synchronisation sequence and compare it with the failing sequence.
If the defined synchronisation changes the result, inspect publication ordering, ownership and coherency configuration; the experiment narrows the search but is not a proof of one root cause.
Adding barriers everywhere instead of fixing attribute/domain config.
Ignoring GPU non-coherent path by default.