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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals25
    • Layering & Transaction Model
      • Layering & Transaction Model: Concepts
      • Layering & Transaction Model: Integration
      • Layering & Transaction Model: Debug
      • Layering & Transaction Model: Interview
      • Layering & Transaction Model: Deep Dive
      • Layering & Transaction Model: Worked Examples
    • Handshake & Backpressure
    • Ordering & Outstanding Rules
    • Bandwidth & Latency Budgeting
    • Protocol Fundamentals: Tricky Q&A
  • AMBA Family (APB / AHB / AXI)17
  • Coherence Fabrics (ACE / CHI)17
  • Memory Interfaces (DDR / LPDDR / HBM)17
  • PCIe & CXL17
  • Embedded Peripherals (I2C / SPI / UART)17
  • High-Speed I/O (USB / Ethernet / MIPI)17
  • Protocol Verification & Compliance17
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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←Layering & Transaction Model
  1. Topics
  2. Bus Protocols
  3. Protocol Fundamentals
  4. Layering & Transaction Model
  5. Layering & Transaction Model: Deep Dive
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    Interface ProtocolsAll levels

    Layering & Transaction Model: Deep Dive

    Deep Dive for Layering & Transaction Model.

    Deep dive

    OSI vs silicon layering — what carries over

    Networking OSI layers and silicon protocol layers rhyme but don't map 1:1. Silicon 'transaction layer' is closest to OSI session/presentation: it defines what the transfer means. Channel layer is transport: reliable delivery mechanics. Physical is physical. The useful habit from OSI: never debug a high-layer symptom by tweaking a low layer without evidence.

    Request/response vs streaming models

    Two fundamental transaction shapes appear everywhere. Request/response (AXI, PCIe mem rd/wr): address + completion. Streaming (AXI-Stream, PCIe streaming, video pipelines): ordered data without per-beat addresses. Layering still applies — streams have packet boundaries (TLAST), flow control, and sideband (TUSER) at the transaction layer even without addresses.

    Diagram
    REQUEST/RESPONSE vs STREAMING
    
    Req/Rsp:  AR -> R beats -> done     (identity = ID + addr)
    Stream:   TVALID beats -> TLAST     (identity = TID + packet #)
    
    Both need: flow control, ordering rules, reset behavior

    Reset and clock domains as layer boundaries

    Clock-domain crossings and reset sequencing are integration boundaries. A multi-bit protocol transaction normally crosses through a protocol-aware asynchronous structure; synchronised Gray-coded pointers may be part of an asynchronous FIFO, but are not themselves a general transaction transport. If a master admits work before the destination path is available, the design needs an explicit hold, retry, error or recovery contract.

    • CDC: use protocol-aware FIFOs (AXI CDC), not ad-hoc valid/ready sync.

    • Reset order: document which blocks must be alive before masters issue.

    • Power transition: define quiesce, rejection, retention, isolation and recovery behaviour for in-flight and newly offered transactions.

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    See also

    • Layering & Transaction Model: Concepts
    • Layering & Transaction Model: Integration
    • Layering & Transaction Model: Debug