CPU0 and DMA0 use the core course's 64-bit AXI4 data, 32-bit byte addresses and four-bit IDs. CPU0 uses ID 1; DMA0 uses repeated ID 3 and independent ID 7. APB is 32-bit behind APB_BRIDGE. The physical reference clocks are clk_sys=100 MHz and clk_per=50 MHz, but this event model does not simulate their phase, CDC circuitry, metastability or cycle latency. Its milestone order is causal; it is not a waveform or cycle-accurate bridge.
The model permits one CPU0 write at a time, retains one accepted AW and one early W beat, and represents one pending bridge command. DMA0 read queues have four slots per ID, though this exercise admits at most two reads on ID 3 before returning data. It does not establish admission or progress for traffic beyond those bounds.
What to notice
A submitted write, accepted AXI parts, APB completion and accepted B are different observations.
The expected read queues come from accepted requests, not a hidden address field on R.
Region / field | Address / value | Exercise contract |
|---|---|---|
SRAM0 | 0x2000_0000–0x2000_FFFF | Read-only during this exercise; aligned eight-byte reads. |
APB window | 0x4000_0000–0x4000_FFFF | Only the LEN_BYTES access below is modelled through target completion. |
DMA_CFG.LEN_BYTES | 0x4000_0008; reset value 0 | CPU0 writes 16 using AWLEN=0, AWSIZE=2, WSTRB=0x0F and WLAST=1. |
Initial SRAM words | At offsets 0, 8, 16, 24: 0x11, 0x22, 0x33, 0x44 | Explicit override of the shared model's zero initial data for this exercise; all are 64-bit words. |
Unmapped probe | 0x5000_0000 | Default AXI target returns DECERR; no mapped peripheral was accessed. |
Other DMA registers, START/BUSY/DONE/IRQ, the peripheral FIFO, real DMA copies, arbitrary bursts and error recovery are outside the executable subset. Do not infer that writing LEN_BYTES alone starts the DMA. DMA0 reads here are independently supplied test traffic.
CPU0 offers W with value 16, encounters backpressure, then its single W beat and AW are accepted. Early W is legal in this model because it can be retained.
The bridge delivers one command to DMA_CFG. An APB SETUP and waiting ACCESS precede one successful completion, which updates LEN_BYTES to 16. The response returns and is accepted once.
DMA0 accepts A=(ID 3, SRAM0+0), B=(ID 3, SRAM0+8), C=(ID 7, SRAM0+16). C may return before A; within ID 3, A precedes B. Expected data is 0x33, then 0x11, then 0x22 for the chosen legal order.
CPU0's unmapped probe returns DECERR. A successful mapped register read would establish a different boundary.
A later DMA0 read is pending when all model participants enter coordinated reset. The chosen policy cancels it, clears protocol bookkeeping and LEN_BYTES, retains SRAM contents, and waits for every participant's reset-release acknowledgement before new traffic. No pre-reset response may enter the new epoch. This is a chosen system policy, not a universal AXI reset-completion guarantee.
After release, DMA0 reuses ID 3 for SRAM0+8 and receives 0x22. An epoch is observer context, not an extra AXI R signal. Diagnostic history is retained outside the modelled reset so a prior failure is not erased.
Case | Observed symptom | Your deliverable |
|---|---|---|
A | A write response is visible at an unexpected point in the request timeline. | Separate offer, acceptance and completion. |
B | The intended register value and completed target value differ. | Follow the same offered and accepted bytes across boundaries. |
C | Concurrent reads finish, but values are associated unexpectedly. | Reconstruct the live requests from accepted AR events. |
D | An out-of-map access appears to succeed. | Identify the requested address and the required response boundary. |
E | Activity appears after restart before the expected new request. | Account for outstanding work and the stated reset policy. |
For each case, retain the first observation that distinguishes a violated obligation from an unproven hypothesis. Do not change a timeout, memory oracle or checker merely to suppress the report.