Explain five failing observations across a CPU register path, DMA read queues, address decoding and coordinated reset. Reconstruct accepted work, identify the first violated obligation, and propose a correction with a regression that also preserves legal traffic.
This lab is a plain SystemVerilog transaction/event model. It is not a full CPU/DMA RTL simulation, a physical asynchronous bridge, or a protocol-compliance suite. You can inspect and run it with a SystemVerilog simulator; no UVM library is required.
1. Brief: model, expected behaviour and symptoms
2. Evidence pack: investigate without the implementation
3. Submission and validation contract
4. Solutions and executable source — spoilers
Bridge, decode and reset walkthrough
Sampled checker and queue exercises
Finish a written diagnosis before opening Solutions. No new course progress or grading feature is required: retain your trace, explanation and regression notes yourself.