These are hand-constructed teaching trace fixtures for the default initial data, not captured simulator waveforms or claimed run results. Each case is independent and starts from the Brief's initial state. Only relevant milestones are shown; gaps do not specify elapsed cycles, and the excerpt does not prove unshown behaviour. Retain alternative hypotheses until the full trace distinguishes them.
R records contain RID/data/status as stated; request addresses in AR records belong to stored observer context. Labels A/B/C on accepted requests are notebook labels only, not response fields.
Milestone | Observed fields |
|---|---|
Offer | WVALID=1, WREADY=0, WDATA=0x10; no AW accepted yet. |
Next sample | WVALID=1, WREADY=0; BVALID=1, BREADY=0; no AW accepted yet. |
Later | W and AW eventually accept; APB access and one B handshake complete. |
Record which observations are already sufficient and which later outcomes do not settle the earlier obligation.
Milestone | Observed fields |
|---|---|
Offer | WVALID=1, WREADY=0, WDATA=0x10, WSTRB=0x0F, WLAST=1. |
Next sample | WVALID=1, WREADY=0, WDATA=0x00; same strobes and WLAST. |
Acceptance | WVALID=1, WREADY=1, WDATA=0x00; AW arrives afterwards. |
Target completion | APB succeeds; LEN_BYTES=0 rather than the intended 16. |
Compare the earliest changed observation with the eventual target result. Do not infer the internal storage element from this boundary evidence alone.
Milestone | Accepted event |
|---|---|
A | ARID=3, ARADDR=0x2000_0000 |
B | ARID=3, ARADDR=0x2000_0008 |
C | ARID=7, ARADDR=0x2000_0010 |
First R | RID=7, RDATA=0x33, RLAST=1, RRESP=OKAY |
Second R | RID=3, RDATA=0x22, RLAST=1, RRESP=OKAY |
Third R | RID=3, RDATA=0x11, RLAST=1, RRESP=OKAY |
Draw the expected queues after every acceptance. The response data is evidence to check, not permission to choose any pending entry that happens to match.
Milestone | Observed fact |
|---|---|
CPU probe | Requested byte address 0x5000_0000, outside both mapped windows. |
Response classification | Returned RRESP=OKAY. |
Mapped controls | SRAM0 and DMA_CFG address-class probes remain mapped. |
Identify the contract for this address before proposing a target-register change. These facts do not locate the exact internal decode gate.
Milestone | Observed event |
|---|---|
Before reset | DMA0 AR accepted: ID 3, SRAM0+0; no response yet. |
Reset | All participants acknowledge the Brief's coordinated cancellation/reset policy. |
After release, before new AR | RID=3, RDATA=0x11, RLAST=1, RRESP=OKAY accepted. |
New traffic | AR ID 3 at SRAM0+8, then R ID 3 with 0x22. |
Account for the pre-reset request and the interval before new traffic. Do not invent a wire-level epoch field to explain the observation.