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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals61
  • AMBA Family (APB / AHB / AXI)61
  • Coherence Fabrics (ACE / CHI)61
  • Memory Interfaces (DDR / LPDDR / HBM)61
  • PCIe & CXL61
  • Embedded Peripherals (I2C / SPI / UART)61
  • High-Speed I/O (USB / Ethernet / MIPI)61
  • Protocol Verification & Compliance61
    • VIP & Agent Architecture
    • Scoreboard & Checker Strategy
    • Compliance & Coverage Plan
      • Compliance & Coverage Plan: Mechanism
      • Compliance & Coverage Plan: Inputs & Outputs
      • Compliance & Coverage Plan: Reports & Metrics
      • Compliance & Coverage Plan: Debug Playbook
      • Compliance & Coverage Plan: Worked Example
      • Compliance & Coverage Plan: Pitfalls & Red Flags
      • Compliance & Coverage Plan: Interview Drills
      • Compliance & Coverage Plan: Review Checklist
      • Compliance & Coverage Plan: Theory Deep Dive
      • Compliance & Coverage Plan: Design Space
      • Compliance & Coverage Plan: Expanded Case Study
      • Compliance & Coverage Plan: Step-by-Step Walkthrough
      • Compliance & Coverage Plan: Comparison Matrix
      • Compliance & Coverage Plan: Software / Programmer View
      • Compliance & Coverage Plan: Silicon PPA Impact
    • Protocol Waveform Debug
    • Protocol Verification & Compliance: Tricky Q&A
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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‹Compliance & Coverage Plan
  1. Topics
  2. Bus Protocols
  3. Protocol Verification & Compliance
  4. Compliance & Coverage Plan
  5. Compliance & Coverage Plan: Debug Playbook

Interface Protocols · All levels

Compliance & Coverage Plan: Debug Playbook

Debug Playbook for Compliance & Coverage Plan.

On this page

    Debug playbook

    Debug Playbook for Compliance & Coverage Plan focuses on spec feature coverage, compliance pass rate, waiver count. The goal is to connect the observable symptom to protocol mechanism, ownership, and regression risk.

    Protocol debug is a search for the FIRST deviation, not the loudest symptom. Timeouts and error flags are usually many cycles downstream of the real cause.

    Root-cause tree

    Diagram
    ROOT-CAUSE TREE — Compliance & Coverage Plan
    
    spec feature coverage, compliance pass rate, waiver count looks wrong
            |
       reproducible?
         /        \
       no          yes
       |            |
     flaky env   same first transaction every time?
     / seed         /            \
                  yes             no
                   |               |
            protocol rule     timing/reset/PVT
            or config bug     or load-dependent
    1. Freeze the failing seed, firmware tag, and spec revision.

    2. Find the first bad transaction, not the loudest downstream timeout.

    3. Map the transaction to signals and VIP monitor events.

    4. Classify the failure: protocol rule, integration config, timing/reset, or performance pressure.

    5. Prove the mechanism with one reduced sequence.

    6. Patch the smallest owner-controlled boundary and rerun compliance plus workload traffic.

    Review memo template

    Diagram
    STAFF PROTOCOL REVIEW MEMO — Protocol Verification & Compliance / Compliance & Coverage Plan
    
    1. Symptom
       - Watched metric: spec feature coverage, compliance pass rate, waiver count
       - Failing interface: <master/slave/endpoint/controller/PHY>
       - Transaction identity: <ID/tag/address/endpoint/lane>
       - Repro setup: <sim/emulation/FPGA/silicon + firmware tag>
    
    2. Mechanism hypothesis
       - Primary mechanism: compliance maps spec requirements to tests, assertions, coverage bins, exclusions, and signed waivers.
       - Competing hypothesis: <timing, reset, bridge, ordering, firmware, or VIP issue>
       - Missing evidence: <waveform, analyzer trace, counter, spec clause, or log>
    
    3. Proposed action
       - Minimal reversible change: <RTL, register setting, bridge config, scheduler, VIP check>
       - Expected metric movement: <delta and workload>
       - Regression risk: ordering, compatibility, performance, power, area, or timing
    
    4. Signoff
       - Re-run artifact: requirement trace matrix, coverage dashboard, waiver log
       - Required owners: verification lead, IP owner, signoff owner
       - Final decision: fix, waive, document limitation, or escalate to architecture

    Protocol deep dive

    Verification closes the gap between 'works in directed test' and 'legal under all stressed traffic'.

    Concept diagram

    Diagram
    VERIFICATION CLOSURE LOOP
    
    spec clause -> test -> assertion -> coverage -> waiver -> signoff
                      ^                           |
                      +--------- gap found --------+

    Metric graph

    Diagram
    COVERAGE vs ESCAPE RATE
    
    escapes
      |*
      | *
      |  *
      |   **  <- knee: more random helps
      |     ****
      +----------------> constrained-random depth

    Metrics and artifacts to collect

    • compliance pass rate

    • coverage closure

    • scoreboard mismatch rate

    • assertion fire count

    • waiver log

    Mini case study

    Block passed VIP compliance but chip failed: system test omitted cross-master ID reuse through a bridge. Scoreboard key did not include upstream port ID.

    Debug branches

    • If VIP pass but silicon fail, check integration assumptions.

    • If scoreboard noisy, fix key (ID+port+addr).

    • If coverage plateau, add compliance gap analysis not more repeats.

    Senior review question

    Ask: what is the first transaction that deviates, and which spec rule does it test?

    Key takeaways

    • Connect every protocol claim to a transaction identity and measurable metric.

    • Store the artifact (waveform, log, counter) next to every signoff decision.

    Common pitfalls

    • Debugging timeouts without finding the first bad transaction.

    • Quoting peak bus width without payload efficiency and retry overhead.

    • Treating VIP compliance as a substitute for system integration replay.

    Principal review addendum

    Re-read Compliance & Coverage Plan against one concrete product workload, not a synthetic directed test.

    compliance maps spec requirements to tests, assertions, coverage bins, exclusions, and signed waivers.

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    See also

    • Compliance & Coverage Plan: Mechanism
    • Compliance & Coverage Plan: Inputs & Outputs
    • Compliance & Coverage Plan: Pitfalls & Red Flags