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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals61
  • AMBA Family (APB / AHB / AXI)61
  • Coherence Fabrics (ACE / CHI)61
  • Memory Interfaces (DDR / LPDDR / HBM)61
  • PCIe & CXL61
  • Embedded Peripherals (I2C / SPI / UART)61
  • High-Speed I/O (USB / Ethernet / MIPI)61
  • Protocol Verification & Compliance61
    • VIP & Agent Architecture
    • Scoreboard & Checker Strategy
    • Compliance & Coverage Plan
      • Compliance & Coverage Plan: Mechanism
      • Compliance & Coverage Plan: Inputs & Outputs
      • Compliance & Coverage Plan: Reports & Metrics
      • Compliance & Coverage Plan: Debug Playbook
      • Compliance & Coverage Plan: Worked Example
      • Compliance & Coverage Plan: Pitfalls & Red Flags
      • Compliance & Coverage Plan: Interview Drills
      • Compliance & Coverage Plan: Review Checklist
      • Compliance & Coverage Plan: Theory Deep Dive
      • Compliance & Coverage Plan: Design Space
      • Compliance & Coverage Plan: Expanded Case Study
      • Compliance & Coverage Plan: Step-by-Step Walkthrough
      • Compliance & Coverage Plan: Comparison Matrix
      • Compliance & Coverage Plan: Software / Programmer View
      • Compliance & Coverage Plan: Silicon PPA Impact
    • Protocol Waveform Debug
    • Protocol Verification & Compliance: Tricky Q&A
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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‹Compliance & Coverage Plan
  1. Topics
  2. Bus Protocols
  3. Protocol Verification & Compliance
  4. Compliance & Coverage Plan
  5. Compliance & Coverage Plan: Interview Drills

Interface Protocols · All levels

Compliance & Coverage Plan: Interview Drills

Interview Drills for Compliance & Coverage Plan.

On this page

    Interview drills

    Interview Drills for Compliance & Coverage Plan focuses on spec feature coverage, compliance pass rate, waiver count. The goal is to connect the observable symptom to protocol mechanism, ownership, and regression risk.

    Diagram
    PROMPT
    You see spec feature coverage, compliance pass rate, waiver count on Compliance & Coverage Plan. Walk through root cause and fix.
    
    STRONG ANSWER
    1. Names the layer and transaction identity.
    2. Explains compliance maps spec requirements to tests, assertions, coverage bins, exclusions, and signed waivers.
    3. Requests requirement trace matrix, coverage dashboard, waiver log.
    4. Proposes one reduced sequence and one system regression.
    
    WEAK ANSWER
    Jumps to widening the interface, increasing FIFO depth, or blaming firmware without evidence.

    Diagram to draw on the whiteboard

    Requirement-to-coverage trace

    Diagram
    COMPLIANCE TRACE MATRIX
    
    spec clause ──> test(s) ──> assertion(s) ──> coverage bin ──> status
      4.2.1          t_axi_07     a_resp_ok        cov_resp        PASS
      4.3.5          t_axi_12     a_order          cov_order       WAIVED (id=W3)
      4.4.0          (none)        (none)           (none)          GAP  <- find these
    
    A gap row is the most valuable output of the plan.

    Root-cause tree to narrate

    Diagram
    ROOT-CAUSE TREE — Compliance & Coverage Plan
    
    spec feature coverage, compliance pass rate, waiver count looks wrong
            |
       reproducible?
         /        \
       no          yes
       |            |
     flaky env   same first transaction every time?
     / seed         /            \
                  yes             no
                   |               |
            protocol rule     timing/reset/PVT
            or config bug     or load-dependent

    Protocol deep dive

    Verification closes the gap between 'works in directed test' and 'legal under all stressed traffic'.

    Concept diagram

    Diagram
    VERIFICATION CLOSURE LOOP
    
    spec clause -> test -> assertion -> coverage -> waiver -> signoff
                      ^                           |
                      +--------- gap found --------+

    Metric graph

    Diagram
    COVERAGE vs ESCAPE RATE
    
    escapes
      |*
      | *
      |  *
      |   **  <- knee: more random helps
      |     ****
      +----------------> constrained-random depth

    Metrics and artifacts to collect

    • compliance pass rate

    • coverage closure

    • scoreboard mismatch rate

    • assertion fire count

    • waiver log

    Mini case study

    Block passed VIP compliance but chip failed: system test omitted cross-master ID reuse through a bridge. Scoreboard key did not include upstream port ID.

    Debug branches

    • If VIP pass but silicon fail, check integration assumptions.

    • If scoreboard noisy, fix key (ID+port+addr).

    • If coverage plateau, add compliance gap analysis not more repeats.

    Senior review question

    Ask: what is the first transaction that deviates, and which spec rule does it test?

    Key takeaways

    • Connect every protocol claim to a transaction identity and measurable metric.

    • Store the artifact (waveform, log, counter) next to every signoff decision.

    Common pitfalls

    • Debugging timeouts without finding the first bad transaction.

    • Quoting peak bus width without payload efficiency and retry overhead.

    • Treating VIP compliance as a substitute for system integration replay.

    Interview whiteboard

    Draw layers first, then place the failing transaction on the diagram.

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    See also

    • Compliance & Coverage Plan: Mechanism
    • Compliance & Coverage Plan: Inputs & Outputs
    • Compliance & Coverage Plan: Reports & Metrics