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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals25
  • AMBA Family (APB / AHB / AXI)17
  • Coherence Fabrics (ACE / CHI)17
  • Memory Interfaces (DDR / LPDDR / HBM)17
  • PCIe & CXL17
  • Embedded Peripherals (I2C / SPI / UART)17
  • High-Speed I/O (USB / Ethernet / MIPI)17
  • Protocol Verification & Compliance17
    • VIP & Agent Architecture
      • VIP & Agent Architecture: Concepts
      • VIP & Agent Architecture: Integration
      • VIP & Agent Architecture: Debug
      • VIP & Agent Architecture: Interview
    • Scoreboard & Checker Strategy
    • Compliance & Coverage Plan
    • Protocol Waveform Debug
    • Protocol Verification & Compliance: Tricky Q&A
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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←VIP & Agent Architecture
  1. Topics
  2. Bus Protocols
  3. Protocol Verification & Compliance
  4. VIP & Agent Architecture
  5. VIP & Agent Architecture: Concepts
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    Interface ProtocolsAll levels

    VIP & Agent Architecture: Concepts

    Concepts for VIP & Agent Architecture.

    Core concepts

    VIP agent structure

    A protocol VIP agent contains: sequencer (generates transaction-level stimulus), driver (converts transactions to pin activity), monitor (observes pins and reconstructs transactions), and checker (validates protocol rules on observed transactions).

    Passive VIP monitors bus activity without driving. Active VIP drives and monitors. Use passive at chip level where real masters exist; active at block level where you need stimulus.

    Diagram
    UVM PROTOCOL AGENT
    
    sequencer --> driver --> DUT pins
                    |
    monitor <--- DUT pins
       |
       +--> checker (protocol rules)
       +--> coverage (bins)
       +--> scoreboard (if connected)

    What VIP evidence covers—and what it does not

    A VIP pass means its enabled checkers observed no violation for the monitored signals, interval, configuration and assumptions. It does not by itself establish unobserved protocol behaviours, functionality, the system address map, firmware configuration or cross-interface ordering.

    A block-level pass followed by a chip-level failure means the existing evidence did not cover the failing condition. Compare boundaries, configuration, traffic, resets, clocks, power states, bridges and reference-model assumptions before calling it an integration gap or a VIP defect.

    • Configure VIP to match implemented spec version and feature subset.

    • VIP parameters (data width, ID width, outstanding depth) must match DUT.

    • Choose active or passive roles from who owns stimulus at that boundary; chip-level environments can use either when the connection and ownership contract permit.

    Key takeaways

    • Configure VIP to match implemented spec version and feature subset.

    • VIP parameters (data width, ID width, outstanding depth) must match DUT.

    • Choose active or passive roles from who owns stimulus at that boundary; chip-level environments can use either when the connection and ownership contract permit.

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    See also

    • VIP & Agent Architecture: Debug
    • VIP & Agent Architecture: Interview