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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals25
  • AMBA Family (APB / AHB / AXI)17
  • Coherence Fabrics (ACE / CHI)17
  • Memory Interfaces (DDR / LPDDR / HBM)17
  • PCIe & CXL17
  • Embedded Peripherals (I2C / SPI / UART)17
  • High-Speed I/O (USB / Ethernet / MIPI)17
  • Protocol Verification & Compliance17
    • VIP & Agent Architecture
      • VIP & Agent Architecture: Concepts
      • VIP & Agent Architecture: Integration
      • VIP & Agent Architecture: Debug
      • VIP & Agent Architecture: Interview
    • Scoreboard & Checker Strategy
    • Compliance & Coverage Plan
    • Protocol Waveform Debug
    • Protocol Verification & Compliance: Tricky Q&A
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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←VIP & Agent Architecture
  1. Topics
  2. Bus Protocols
  3. Protocol Verification & Compliance
  4. VIP & Agent Architecture
  5. VIP & Agent Architecture: Debug
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    Interface ProtocolsAll levels

    VIP & Agent Architecture: Debug

    Debug for VIP & Agent Architecture.

    Primary debug scenario

    Symptom: Block passes VIP compliance. Chip fails system test with data corruption on same interface.

    Triage steps

    1. Compare VIP configuration: block vs chip (width, ID, address map).

    2. Check if chip test uses same traffic as block test.

    3. Add passive VIP monitor at chip boundary — does it flag errors?

    4. Trace failing transaction through bridge/fabric not present in block test.

    5. Check firmware init sequence — block test may skip this.

    Common pitfalls

    • Closing bug as 'VIP issue' when integration differs.

    • VIP pass without system-level replay.

    • Block-level scoreboard key missing port/bridge ID.

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    See also

    • VIP & Agent Architecture: Concepts