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Course contents

  • How to Use This Course
  • Reading Path
  • STA Glossary
  • STA Metrics Reference
  • STA Mastery Cheatsheet
  • Timing Paths and Checks16
  • Constraints & SDC Fundamentals20
  • Delay Graph & Path Analysis16
  • Beyond Setup and Hold16
  • Multi-Corner Multi-Mode Signoff16
  • OCV, AOCV, POCV and Variation16
  • Crosstalk and Noise16
  • ECO and Closure16
  • STA Debug Playbook16
  • STA Interview Prep26
    • STA Whiteboard Framework
    • STA Framework Drills
      • Drill Set: Fundamentals
      • Drill Set: Constraints
      • Drill Set: Signoff
    • Scenario: MMMC Storm
    • Scenario: ECO Under Pressure
    • Scenario: Constraint Ghost
    • STA Interview Q&A Bank
    • STA Interview Q&A Bank (Expanded)
  • Capstone Timing Signoff Lab4
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‹STA Framework Drills
  1. Topics
  2. Static Timing Analysis
  3. STA Interview Prep
  4. STA Framework Drills
  5. Drill Set: Constraints

Part 10 · Interview Prep · All levels

Drill Set: Constraints

Six 90-second prompts on multicycle hold, generated clocks, input and output delays, max-delay exceptions and exception coverage.

On this page

    How to run it

    Same routine: cover the answers, 90 seconds each, framework steps aloud. For constraints questions the evidence step is usually a path count or a coverage report.

    #

    Prompt

    Answer

    1

    A 3-cycle setup multicycle on one clock. What hold exception value restores the hold check?

    2 (N - 1)

    2

    A divide-by-4 generated clock from a 2.0 ns source. Its period?

    8.0 ns

    3

    Input delay 2.0 ns on a 5.0 ns clock; internal path 1.8 ns; setup 0.10 ns. Slack?

    +1.10 ns: 5.0 - 2.0 - 1.8 - 0.10

    4

    Output delay 1.2 ns on a 4.0 ns clock; internal path (clock-to-Q plus logic) 2.3 ns. Slack?

    +0.50 ns: 4.0 - 1.2 - 2.3

    5

    A maximum-delay constraint of 3.0 ns on a path that takes 3.4 ns. Slack?

    -0.40 ns: the check is against the constraint, not a clock edge

    6

    A false path covers 1120 paths; you expected 2. What do you do?

    Count and list the extra paths, scope the exception with a through-point, and re-run: the exception is far broader than intended

    example.py
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    def r(x): return round(x, 3)
    hold_value = 3 - 1
    period = 4 * 2.0
    a3 = 5.0 - 2.0 - 1.8 - 0.10
    a4 = 4.0 - 1.2 - 2.3
    a5 = 3.0 - 3.4
    ratio = 1120 / 2
    assert hold_value == 2 and period == 8.0
    assert [r(a3), r(a4), r(a5)] == [1.1, 0.5, -0.4]
    assert ratio == 560.0
    print("PASS: hold value", hold_value, "period", period, "slacks", [r(a3), r(a4), r(a5)], "coverage ratio", ratio)
    Diagram
    # not-run: SDC is not executable here
    set_multicycle_path 3 -setup -from [get_clocks clk] -to [get_pins u_slow/*/D]
    set_multicycle_path 2 -hold  -from [get_clocks clk] -to [get_pins u_slow/*/D]
    create_generated_clock -name clk_div4 -source [get_ports clk] -divide_by 4 [get_pins u_div/q_reg/Q]

    What a strong delivery adds

    • Prompt 1: says why the hold value is N-1 (the hold edge follows the setup edge) and what the default does if you forget it.

    • Prompt 3 and 4: states that input and output delays model the external logic and clock, and which clock they are relative to.

    • Prompt 5: notes that a maximum-delay path ignores the clock relationship and checks the stated limit.

    • Prompt 6: quotes the count, the risk (a hidden related path) and the scoped fix.

    Common pitfall

    Answering prompt 6 with 'it is probably fine'. An exception covering 560 times the expected paths is wrong until shown otherwise.

    Interview

    When asked about an exception, always ask yourself 'how many paths does it cover'.

    Check yourself In prompt 3, what would the slack be if the input delay were 40% of the period instead of 2.0 ns?

    The same: 40% of 5.0 ns is 2.0 ns, so the slack is +1.10 ns.

    Related topics

    • Drill Set: Fundamentals

    • Next: Drill Set: Signoff

    • Constraints and SDC

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