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Course contents

  • How to Use This Course
  • Reading Path
  • STA Glossary
  • STA Metrics Reference
  • STA Mastery Cheatsheet
  • Timing Paths and Checks16
  • Constraints & SDC Fundamentals20
  • Delay Graph & Path Analysis16
  • Beyond Setup and Hold16
  • Multi-Corner Multi-Mode Signoff16
  • OCV, AOCV, POCV and Variation16
  • Crosstalk and Noise16
  • ECO and Closure16
  • STA Debug Playbook16
  • STA Interview Prep26
    • STA Whiteboard Framework
    • STA Framework Drills
    • Scenario: MMMC Storm
    • Scenario: ECO Under Pressure
      • The Scenario
      • Investigation
      • Root Cause and Fix
      • How to Narrate It
    • Scenario: Constraint Ghost
    • STA Interview Q&A Bank
    • STA Interview Q&A Bank (Expanded)
  • Capstone Timing Signoff Lab4
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‹Scenario: ECO Under Pressure
  1. Topics
  2. Static Timing Analysis
  3. STA Interview Prep
  4. Scenario: ECO Under Pressure
  5. Root Cause and Fix

Part 10 · Interview Prep · All levels

Root Cause and Fix

The cause is a wider path spread from the logic change; the plan inserts delay for the 196 that fit, uses short-branch delay or restructuring for 18, and runs verification in batches.

On this page

    Root cause

    Removing a gate level shortened the minimum paths into a group of flops and left a wider gap between their shortest and longest paths in that cone. For most of those endpoints there is enough setup slack to buy back hold with delay cells. For a minority the gap itself is the problem. The 31 setup violations are separate: they sit in the deeper cone, where the added gate level lengthened the maximum paths.

    The plan

    Step

    Endpoints

    Method

    Rung of the ECO ladder

    1

    196

    Insert delay at the endpoints, within setup slack

    Buffer insertion (rung 3)

    2

    12 of the 18

    Insert delay on the short branch only, ahead of the point where short and long paths merge (a per-path fix, not at the endpoint)

    Buffer insertion (rung 3)

    3

    6 of the 18

    Restructure the logic to narrow the spread between longest and shortest paths without re-adding the removed gate (function unchanged, equivalence checked)

    Logic change (rung 5)

    4

    —

    Verification: fast loop after each batch, two full runs

    Union of all rungs used

    example.py
    1
    2
    3
    4
    5
    6
    7
    8
    9
    10
    11
    counts = {"delay": 196, "short_branch": 12, "logic": 6}
    assert sum(counts.values()) == 214 - 0
    batches = [("delay", 196), ("short_branch", 12), ("logic", 6)]
    hours = 0
    for name, n in batches:
        hours += 5                               # fast loop after each batch
    hours += 2 * 18                              # two full runs
    assert hours == 51
    waived = 214 - sum(counts.values())
    assert waived == 0
    print("PASS: all 214 hold endpoints have a fix:", counts, "; schedule", hours, "h of 60; waivers", waived)

    Every endpoint has a fix: 196 by delay at the endpoints, 12 by delay on the short branch only, ahead of the point where short and long paths merge, and 6 by restructuring the logic to narrow the spread; no waiver is needed. The schedule takes 51 of the 60 hours: three batches each followed by a five-hour fast loop, then two 18-hour full runs. The nine spare hours are the buffer for the batch that goes wrong. The 31 setup violations are handled in the same batches: the slow-corner violations are mostly shared segments of paths touching the added gate level in the deeper cone, so one sizing change covers many of them.

    What not to do

    • Do not waive hold in the fast corner: hold failures are not fixed by lowering the clock frequency.

    • Do not apply all changes in one batch: a failure leaves no time to find the cause.

    • Do not skip the equivalence check on the logic rebalancing: it is the only proof that the functional fix survived.

    Common pitfall

    Fixing the 18 structural endpoints with delay at the endpoints. The sum screen already says that trades hold for setup: those need a per-path or structural fix.

    Interview

    Give the plan as numbers: endpoints by method, hours by loop.

    Check yourself Why is the equivalence check required for the logic rebalancing and not for the delay insertion?

    Delay insertion does not change function; restructuring logic can, so equivalence has to confirm that the functional ECO is intact.

    Related topics

    • Investigation

    • Next: How to Narrate It

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    See also

    • The Scenario