Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutContactPrivacyTerms
Skip to lesson

Course contents

  • How to Use This Course
  • Reading Path
  • STA Glossary
  • STA Metrics Reference
  • STA Mastery Cheatsheet
  • Timing Paths and Checks16
  • Constraints & SDC Fundamentals20
  • Delay Graph & Path Analysis16
  • Beyond Setup and Hold16
  • Multi-Corner Multi-Mode Signoff16
  • OCV, AOCV, POCV and Variation16
  • Crosstalk and Noise16
  • ECO and Closure16
  • STA Debug Playbook16
  • STA Interview Prep26
    • STA Whiteboard Framework
      • The Answer Framework
      • Drawing a Path
      • Naming the Failure
      • Grading Rubric
    • STA Framework Drills
    • Scenario: MMMC Storm
    • Scenario: ECO Under Pressure
    • Scenario: Constraint Ghost
    • STA Interview Q&A Bank
    • STA Interview Q&A Bank (Expanded)
  • Capstone Timing Signoff Lab4
Loading lesson

‹STA Whiteboard Framework
  1. Topics
  2. Static Timing Analysis
  3. STA Interview Prep
  4. STA Whiteboard Framework
  5. Drawing a Path

Part 10 · Interview Prep · All levels

Drawing a Path

A five-element sketch: launch flop, logic, capture flop, the clock edges with their latencies, and arrival and required times on one line.

On this page

    Why it matters

    Drawing turns a verbal question into something you can compute on. A good sketch has five elements and takes thirty seconds. Interviewers watch whether you draw the clock edges, because that is where most mistakes originate.

    The five elements

    Element

    What to write

    Launch flop

    Clock arrival (latency), clock-to-Q

    Logic

    Cell and net delays, summed

    Capture flop

    Clock arrival, setup time (and hold time)

    Clock edges

    Launch edge and capture edge times, so the period or fraction of it is explicit

    Times

    Arrival time at the capture D pin; required time; slack

    A launch flop, combinational logic and a capture flop.
    A whiteboard-style path: write the numbers on the sketch before computing anything.
    example.py
    1
    2
    3
    4
    5
    6
    7
    8
    9
    10
    11
    12
    # Period 1.25 ns. Launch latency 0.30, clk-to-Q 0.40, logic 0.55; capture latency 0.35, setup 0.06, hold 0.05.
    T = 1.25
    launch_lat, cq, logic = 0.30, 0.40, 0.55
    cap_lat, setup, hold = 0.35, 0.06, 0.05
    arrival = launch_lat + cq + logic                       # 1.25
    required = T + cap_lat - setup                          # 1.54
    setup_slack = required - arrival
    min_arrival = launch_lat + 0.30 + 0.20                  # shortest path: clk-to-Q 0.30, logic 0.20
    hold_slack = min_arrival - (cap_lat + hold)
    assert round(arrival, 3) == 1.25 and round(required, 3) == 1.54
    assert round(setup_slack, 3) == 0.29 and round(hold_slack, 3) == 0.40
    print("PASS: setup slack", round(setup_slack, 3), "hold slack", round(hold_slack, 3))

    From the sketch: arrival 1.25 ns (0.30 + 0.40 + 0.55), required 1.54 ns (1.25 + 0.35 - 0.06), setup slack +0.29 ns. For hold, the shortest path arrives at 0.80 ns against 0.40 ns of capture latency plus hold time, giving +0.40 ns. Drawing the capture latency separately is what makes the skew visible: it helped setup by 0.05 ns here and cost hold by the same amount.

    What the interviewer is testing

    • Whether you separate data path from clock paths and include both latencies.

    • Whether you know the capture edge: one period after launch for a same-edge pair, half for opposite edges.

    • Whether you can compute slack from your own sketch without prompting.

    Common pitfall

    Drawing the data path only. Without clock latencies on the sketch, skew and uncertainty are forgotten and the computed slack is wrong.

    Interview

    Write numbers on the drawing and compute out loud; a silent drawing gives the interviewer nothing to grade.

    Check yourself On the sketch, what changes if the capture flop is on the falling edge?

    The capture edge is half a period after launch, so required time is T/2 + cap latency - setup = 0.625 + 0.35 - 0.06 = 0.915 ns, and setup slack becomes -0.335 ns.

    Related topics

    • The Answer Framework

    • Next: Naming the Failure

    Previous

    155 / 183

    Next: Naming the Failure

    Up next

    Up nextNaming the Failure

    Sign in to save progress

    Practice this lessonReport an error

    See also

    • Grading Rubric