Each check has its own cause and its own fix. A candidate who names the check first sounds like a signoff engineer. A candidate who says 'timing violation' and moves to a fix usually picks the wrong one for a hold or a clocking problem.
Symptom | Check | First question |
|---|---|---|
Negative slack, data path long | Setup | Where is the delay, and is it shared by other failing paths? |
Negative slack, short path, fast corner | Hold | Skew or short logic? Is there setup slack to spend? |
Violation on an asynchronous reset pin | Recovery or removal | Is the release synchronised in this domain? |
Violation on a clock gate enable | Clock gating check | Which phase does the enable change in? |
Violation on a clock pin width | Minimum pulse width or period | Is the duty cycle distorted, or the clock too fast for the macro? |
Big numbers that look wrong | Constraint or setup problem | Is the same path analysed with the right edges, exceptions and clocks? |
def name_check(sym):
rules = [
(lambda s: s["pin"] == "gate_enable", "clock gating"),
(lambda s: s["pin"] == "clock_pin", "pulse width / min period"),
(lambda s: s["pin"] in ("async_reset", "async_set"), "recovery/removal"),
(lambda s: s["pin"] == "data" and s["kind"] == "min", "hold"),
(lambda s: s["pin"] == "data" and s["kind"] == "max", "setup"),
]
for cond, name in rules:
if cond(sym):
return name
return "constraint or setup problem"
tests = [({"pin": "data", "kind": "max"}, "setup"), ({"pin": "data", "kind": "min"}, "hold"),
({"pin": "async_reset", "kind": "max"}, "recovery/removal"), ({"pin": "gate_enable", "kind": "max"}, "clock gating"),
({"pin": "gate_enable", "kind": "min"}, "clock gating"),
({"pin": "clock_pin", "kind": "max"}, "pulse width / min period"), ({"pin": "other", "kind": "max"}, "constraint or setup problem")]
assert all(name_check(s) == n for s, n in tests)
print("PASS: classifier covers", len(tests), "symptom classes")The classifier is trivial on purpose: the receiving pin and the min or max nature of the path already name the check in most cases. The skill is to say it aloud first: 'This is a hold failure on a data pin in the fast corner', and then ask the question in the table's third column. If none of the rows fits, suspect the setup of the analysis before the design.
Whether you separate the families of check.
Whether you ask a diagnostic question rather than recite a fix list.
Whether you know to suspect constraints when numbers look wrong.
Minimum pulse width: is the duty cycle at that pin distorted in that corner (one phase narrow), or is the clock simply too fast for the macro (both phases failing)?