Eight flops sampling one bus share one clock net. That net has a fanout of 8 before any repair, and larger designs reach hundreds of sinks.
The script below builds that net and pins the flop count after generic passes. It proves the shared structure, not any particular buffering.
read_verilog <<EOV
module highfan(input wire clk, input wire [7:0] d, output reg [7:0] q);
always @(posedge clk) q[0] <= d[0];
always @(posedge clk) q[1] <= d[1];
always @(posedge clk) q[2] <= d[2];
always @(posedge clk) q[3] <= d[3];
always @(posedge clk) q[4] <= d[4];
always @(posedge clk) q[5] <= d[5];
always @(posedge clk) q[6] <= d[6];
always @(posedge clk) q[7] <= d[7];
endmodule
EOV
hierarchy -check -top highfan
proc
opt
select -assert-count 8 t:$dff
log PASS: one clock net fans out to 8 flopsA tree of branch b covers b^s sinks in s stages. The EXAMPLE below uses branch 4 for 64 sinks.
64 sinks, branch 4: 4 x 4 x 4 = 64, so 3 stages
100 sinks, branch 4: 64 < 100 <= 256 = 4^4, so 4 stagesEach stage holds one buffer per group of b sinks. Areas are library units of the fictional course.lib, where BUF costs 2.
buffers per level: 64 / 4 = 16, 16 / 4 = 4, 4 / 4 = 1
total buffers = 16 + 4 + 1 = 21
area = 21 x 2 = 42 area units (BUF = 2 in course.lib)
each first-level buffer drives 64 / 16 = 4 sinksThe program below replays the stage count, the buffer count and the area. Its checks use exact integer steps, not floating point.
import sys
def stages(fans, branch):
covered = 1
n = 0
while covered < fans:
covered = covered * branch
n = n + 1
return n
def tree_bufs(fans, branch):
total = 0
level = fans
while level > 1:
level = level // branch
total = total + level
return total
BUF_AREA = 2
checks = [
(stages(64, 4), 3),
(stages(100, 4), 4),
(tree_bufs(64, 4), 21),
(tree_bufs(64, 4) * BUF_AREA, 42),
(64 // 16, 4),
]
for i in range(len(checks)):
got, want = checks[i]
if got != want:
print("FAIL: check " + str(i + 1) + " got " + str(got) + " want " + str(want))
sys.exit(1)
print("PASS: tree math gives 3 stages, 21 buffers and 42 area units")3 stages: 16, then 4, then 1 buffer. That sums to 21 buffers.
Three stages cover only 64 sinks. The fourth stage reaches 256, which is the first power of 4 above 100.