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Course contents

  • Logic Synthesis Glossary
  • Logic Synthesis Cheatsheet
  • Synthesis Foundations14
  • Logic Optimisation and Mapping20
    • Boolean Optimisation
    • Technology Mapping
    • Cell Libraries and Liberty
    • Structuring and Buffering
      • Fanout, Slew and Capacitance Rules
      • Delay of a Driver with Load
      • Buffer Trees
      • Sizing, Cloning and Restructuring
      • Fanout Constraints in Practice
  • Constraints and Timing15
  • Sequential, FSM and Memory19
  • Datapath Synthesis14
  • Area, Power and Test14
  • Verification, ECO and Handoff15
  • Flows and Debugging15
  • Interview and Judgment11
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‹Structuring and Buffering
  1. Topics
  2. Logic Synthesis
  3. Logic Optimisation and Mapping
  4. Structuring and Buffering
  5. Delay of a Driver with Load

Part 2 · Logic Optimisation and Mapping · Intermediate

Delay of a Driver with Load

Driver delay from load with an EXAMPLE delay table and runnable model.

On this page

    The delay-table form

    A library delay table gives cell delay against input slew and load capacitance. This lesson fixes the slew and reads delay against load only.

    The EXAMPLE table below is linear: delay equals a base plus a slope times load. Real tables curve, so this form is a teaching stand-in.

    D=d0​+k⋅Cload​

    Load (EXAMPLE fF)

    Delay (EXAMPLE ns)

    1

    0.5

    2

    0.7

    4

    1.1

    8

    1.9

    A worked loaded driver

    Take 2 fF of wire plus 1 fF per sink. The calc block compares 1 sink against 8 sinks.

    Diagram
    EXAMPLE table at fixed input slew: d = 0.3 + 0.2 x C, EXAMPLE ns and EXAMPLE fF
    1 sink:  C = 2 + 1 x 1 = 3 fF,   d = 0.3 + 0.2 x 3 = 0.9 ns
    8 sinks: C = 2 + 8 x 1 = 10 fF,  d = 0.3 + 0.2 x 10 = 2.3 ns
    extra delay from 7 more sinks = 2.3 - 0.9 = 1.4 ns

    A runnable delay model

    The program below implements the EXAMPLE table. Its five self-checks replay the rows and the worked driver.

    example.py
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    import sys
    
    D0 = 0.3
    K = 0.2
    
    def driver_delay(load_ff):
        return D0 + K * load_ff
    
    def close(got, want):
        return abs(got - want) < 1e-9
    
    checks = [
        (driver_delay(1), 0.5),
        (driver_delay(3), 0.9),
        (driver_delay(4), 1.1),
        (driver_delay(8), 1.9),
        (driver_delay(10), 2.3),
    ]
    
    for i in range(len(checks)):
        got, want = checks[i]
        if not close(got, want):
            print("FAIL: check " + str(i + 1) + " got " + str(got) + " want " + str(want))
            sys.exit(1)
    
    print("PASS: delay model matches the table on 5 loads")

    Common mistakes

    Common pitfall

    This table holds input slew fixed, so it understates slow-input cases. A slow edge into the driver stretches the output edge further; the full table has both axes for that reason.

    Interview

    Likely probes: reading delay against load.

    • Delay here is 0.3 plus 0.2 per EXAMPLE fF at the stated slew.

    • Eight sinks instead of one adds 7 fF and 1.4 EXAMPLE ns.

    • The five self-checks replay the table rows exactly.

    Check yourself The EXAMPLE table gives d = 0.3 + 0.2 x C. What is the delay at 4 fF?

    1.1 EXAMPLE ns: 0.3 + 0.8. That row sits in both the table and the program checks.

    Check yourself All five program checks pass. What does that prove, and what stays open?

    It proves the code agrees with the hand-worked rows. It leaves open whether the EXAMPLE slope matches any real library.

    Related topics

    • Buffer trees

    • Cell libraries and Liberty

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    See also

    • Sizing, Cloning and Restructuring
    • Fanout Constraints in Practice