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Course contents

  • Logic Synthesis Glossary
  • Logic Synthesis Cheatsheet
  • Synthesis Foundations14
  • Logic Optimisation and Mapping20
    • Boolean Optimisation
    • Technology Mapping
    • Cell Libraries and Liberty
    • Structuring and Buffering
      • Fanout, Slew and Capacitance Rules
      • Delay of a Driver with Load
      • Buffer Trees
      • Sizing, Cloning and Restructuring
      • Fanout Constraints in Practice
  • Constraints and Timing15
  • Sequential, FSM and Memory19
  • Datapath Synthesis14
  • Area, Power and Test14
  • Verification, ECO and Handoff15
  • Flows and Debugging15
  • Interview and Judgment11
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‹Structuring and Buffering
  1. Topics
  2. Logic Synthesis
  3. Logic Optimisation and Mapping
  4. Structuring and Buffering
  5. Fanout, Slew and Capacitance Rules

Part 2 · Logic Optimisation and Mapping · Intermediate

Fanout, Slew and Capacitance Rules

Max fanout, transition and capacitance limits with a worked load sum.

On this page

    Three electrical rules

    A driver sees the wire plus every sink pin as one capacitance load. Larger loads mean slower edges and longer delays.

    Three limits guard the result. Each is stated as a constraint, and each repair in this topic targets one of them.

    Rule

    What it limits

    EXAMPLE limit

    Max fanout

    Sink count on one net

    32 sinks

    Max transition

    Slowest allowed edge (slew)

    0.5 EXAMPLE ns

    Max capacitance

    Total load on one driver

    10 EXAMPLE fF

    How load adds up

    Load is the wire capacitance plus one pin capacitance per sink. The calc block checks an EXAMPLE net against an EXAMPLE limit.

    Diagram
    EXAMPLE limits (illustrative, not any tool's defaults):
    max_capacitance 10 EXAMPLE fF, max_fanout 32 sinks
    EXAMPLE net: wire 4 fF, each sink 1 fF
    6 sinks: 4 + 6 x 1 = 10 fF -> exactly at the limit
    7 sinks: 4 + 7 x 1 = 11 fF -> violates by 1 fF
    40 sinks against max_fanout 32 -> violates by 8 sinks

    Constraints that state the rules

    The three SDC-style commands below are a tool-neutral sketch. The names are standard SDC; the limits are EXAMPLE values.

    Diagram
    # illustrative SDC sketch (not run; EXAMPLE limits, not any tool's defaults)
    set_max_fanout 32 [current_design]
    set_max_transition 0.5 [current_design]
    set_max_capacitance 10 [current_design]

    Common mistakes

    Common pitfall

    A net can pass max fanout yet fail max transition. Long wires add capacitance without adding sinks, so check all three rules on every repaired net.

    Interview

    Likely probes: which rule each repair targets.

    • Buffer trees and cloning split sink count and load across copies.

    • Gate sizing adds drive strength, which shortens edges and stage delay.

    • Restructuring shortens logic depth, which is a delay fix more than a load fix.

    Check yourself An EXAMPLE net has 4 fF of wire and 1 fF per sink against a 10 fF limit. How many sinks fit?

    6 sinks: 4 + 6 = 10 fF, exactly at the limit. The 7th sink reaches 11 fF and violates.

    Check yourself A net drives 40 sinks against max_fanout 32. By how much does it violate, and does fixing that guarantee the slew rule?

    It violates by 8 sinks. No: the repaired net must still be checked against max transition and max capacitance.

    Related topics

    • Delay of a driver with load

    • RTL for timing

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    See also

    • Buffer Trees
    • Sizing, Cloning and Restructuring
    • Fanout Constraints in Practice