The max_fanout, max_transition and max_capacitance repairs fire only on violations of those limits; timing optimisation may buffer for delay as well. Without those limits, there is no rule violation to repair, though timing work may still add buffers.
The sketch below repeats the lesson-1 limits. It is illustrative: the command names are standard SDC and every number is an EXAMPLE value.
# illustrative SDC sketch (not run; EXAMPLE limits, not any tool's defaults)
set_max_fanout 32 [current_design]
set_max_transition 0.5 [current_design]
set_max_capacitance 10 [current_design]Every repair in this topic spends area to buy back a rule. The table and calc price the fanout-64 tree from the earlier lesson.
Repair | Fixes | Costs |
|---|---|---|
Buffer tree | Fanout, slew and load together | Area, stage delay and power. |
Gate sizing | Slow edges on one stage | Area and power on that cell. |
Cloning | Fanout and load on shared logic | A copy of the cloned logic. |
Restructuring | Logic depth | Area in some arrangements; check each case. |
repair bill for the fanout-64 tree (course.lib area units):
21 BUF x 2 = 42 area units
EXAMPLE power: P = alpha x C x V^2 x f = 0.5 x 2 x 1 x 1 = 1 unit per buffer
21 buffers x 1 = 21 EXAMPLE power units42 area units and 21 power units. Both scale with buffer count, so narrower branches cost more of each.
No. That repair fires only on a violation of its limit. Timing optimisation could still buffer the net for delay, which is a separate decision.