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Course contents

  • Logic Synthesis Glossary
  • Logic Synthesis Cheatsheet
  • Synthesis Foundations14
  • Logic Optimisation and Mapping20
    • Boolean Optimisation
    • Technology Mapping
    • Cell Libraries and Liberty
    • Structuring and Buffering
      • Fanout, Slew and Capacitance Rules
      • Delay of a Driver with Load
      • Buffer Trees
      • Sizing, Cloning and Restructuring
      • Fanout Constraints in Practice
  • Constraints and Timing15
  • Sequential, FSM and Memory19
  • Datapath Synthesis14
  • Area, Power and Test14
  • Verification, ECO and Handoff15
  • Flows and Debugging15
  • Interview and Judgment11
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‹Structuring and Buffering
  1. Topics
  2. Logic Synthesis
  3. Logic Optimisation and Mapping
  4. Structuring and Buffering
  5. Sizing, Cloning and Restructuring

Part 2 · Logic Optimisation and Mapping · Intermediate

Sizing, Cloning and Restructuring

Gate sizing, driver cloning and restructuring, with exact delay math.

On this page

    Gate sizing

    Sizing swaps a cell for a stronger drive-strength sibling with the same function. Stronger drive shortens edges and stage delay at higher area.

    Sizing helps one slow stage, not a deep path. When every stage is slow, the structure is the problem, not the sizes.

    Cloning a driver

    Cloning duplicates the driver so each copy feeds a subset of the sinks. Each copy sees less load, so each edge sharpens.

    The calc block clones a 12-sink EXAMPLE driver into two copies of 6. The delay form is the lesson-2 table.

    Diagram
    EXAMPLE driver: d = 0.3 + 0.2 x C, wire 2 fF, each sink 1 fF
    before: C = 2 + 12 x 1 = 14 fF, d = 0.3 + 0.2 x 14 = 3.1 ns
    after cloning (2 copies, 6 sinks each):
    C = 2 + 6 x 1 = 8 fF, d = 0.3 + 0.2 x 8 = 1.9 ns
    saving = 3.1 - 1.9 = 1.2 ns for twice the driver area

    Optimal branch width

    Wider branches need fewer stages but slower stages. The EXAMPLE below prices branch 2, 4 and 8 for 64 sinks with a stage delay of 2 plus branch.

    Branch 4 wins here at 18 EXAMPLE ns. That optimum moves with the library, so it is an EXAMPLE result, not a rule.

    example.py
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    import sys
    
    FANS = 64
    
    def stages(fans, branch):
        covered = 1
        n = 0
        while covered < fans:
            covered = covered * branch
            n = n + 1
        return n
    
    def tree_delay(branch):
        return stages(FANS, branch) * (2 + branch)
    
    totals = [(2, tree_delay(2)), (4, tree_delay(4)), (8, tree_delay(8))]
    want = [(2, 24), (4, 18), (8, 20)]
    
    for i in range(len(totals)):
        got, want_pair = totals[i], want[i]
        if got != want_pair:
            print("FAIL: branch " + str(got[0]) + " got " + str(got[1]) + " want " + str(want_pair[1]))
            sys.exit(1)
    
    best = min(totals, key=lambda p: p[1])
    if best[0] != 4:
        print("FAIL: best branch got " + str(best[0]) + " want 4")
        sys.exit(1)
    
    print("PASS: branch 4 wins at 18 units against 24 and 20")

    Restructuring for depth

    Balanced trees also cut logic depth. An 8-input AND needs 7 two-input gates either way, but the arrangement sets the depth.

    Diagram
    8-input AND from 2-input AND gates: 8 - 1 = 7 gates either way
    chain: 7 gates in series -> depth 7
    balanced tree: 4 + 2 + 1 gates per level -> depth 3
    same count, depth 3 against 7

    Common mistakes

    Common pitfall

    A clone that still drives every sink fixes nothing. Each copy must own its subset of loads, with no shared tail net rejoining them.

    Interview

    Likely probes: cloning versus sizing, and the branch tradeoff.

    • Cloning splits load across copies; sizing strengthens one driver. Both cost area.

    • Branch 4 wins the EXAMPLE at 18 units against 24 for branch 2 and 20 for branch 8.

    • Restructuring cuts depth without touching load; it pairs with buffering rather than replacing it.

    Check yourself Cloning halves each copy's sinks from 12 to 6 in the EXAMPLE. What are the two delays?

    3.1 EXAMPLE ns before and 1.9 after. The saving is 1.2 ns for twice the driver area.

    Check yourself Why is branch 4 optimal only for this EXAMPLE?

    The totals depend on the stage formula 2 plus branch. A different library slope or base moves the minimum.

    Check yourself An 8-input AND uses 7 gates as a chain of depth 7. What does balancing change, and what stays the same?

    Depth falls from 7 to 3. Gate count stays 7; only the arrangement changes.

    Related topics

    • Fanout constraints in practice

    • Area, power and timing tradeoffs

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    See also

    • Fanout, Slew and Capacitance Rules
    • Delay of a Driver with Load