Senior UVM interviews draw from a surprisingly small pool of questions. The wording changes, the bench in the question changes, but the same sixty or so mechanisms come back in loop after loop. This page lists them by area. Each question links to the one lesson where its answer lives (the course gives every fact one home) and, where there is one, to the interview page that practises it.
Use it two ways. Before a loop, read down a section and answer each question aloud in two sentences; open the home lesson only for the ones you stumbled on. After a loop, find the questions you were actually asked and check your answers against the home lesson.
How does the run phase end, and what is drain time for? Home: set_drain_time deep dive. Practise: concept round.
A test ends at time 0, or after 155 ns, with nothing checked. Why? Home: Early-end playbook. Practise: Debug round, log 2.
A test hangs until the timeout. How do you find who holds the objection? Home: Objection triage and hang forensics. Practise: Debug round, log 1.
When would you use phase_ready_to_end? Home: phase_ready_to_end. Practise: concept round.
Run phase versus the runtime sub-phases; when would you jump phases? Home: Reset phase and phase jump. Practise: concept round.
Why is build top-down and connect bottom-up? Home: Why build_phase is top-down. Practise: concept round.
Two config_db sets for the same field conflict. Which one wins? Home: config_db resolution. Practise: concept round.
Type override versus instance override; two instance overrides match. Which wins? Home: Override resolution. Practise: concept round.
A derived class has no registration macro of its own. What does create() build? Home: Registration macros. Practise: concept round.
A config_db get fails. How do you debug it? Home: The set/get contract. Practise: concept round.
Why use a config object instead of twenty separate knobs? Home: Config objects. Practise: concept round.
+UVM_TESTNAME versus the argument of run_test: which wins? Home: +UVM_TESTNAME and plusargs.
Port, export, imp: which connects to which, and in which direction? Home: connect() rules. Practise: concept round.
Why must a monitor broadcast a fresh object every time? Home: The monitor. Practise: Coding round, drill 2.
imp_decl or analysis FIFOs for a multi-input scoreboard? Home: imp_decl vs FIFOs. Practise: concept round.
In what order do subscribers of an analysis port receive write()? Home: Analysis broadcast. Practise: concept round.
TLM 2.0: when do you use b_transport and when nb_transport? Home: Non-blocking transport. Practise: concept round.
Walk through start_item, finish_item, get_next_item and item_done. Home: The driver handshake. Practise: concept round.
What happens if the driver calls item_done(rsp) and nobody calls get_response? Home: Responses and pipelined drivers. Practise: Coding round, drill 3.
lock versus grab: who gets the sequencer next? Home: lock vs grab. Practise: concept round.
Name the arbitration modes. Where does starvation come from? Home: Inside the sequencer. Practise: concept round.
Do you need a virtual sequencer for a virtual sequence? Home: Virtual sequences without a virtual sequencer. Practise: Coding round, drill 5.
How do you stop sequences cleanly when reset arrives mid-test? Home: Stopping sequences and reset. Practise: concept round.
How do you layer a protocol on another (packets over a bus)? Home: Protocol layering. Practise: concept round.
Active versus passive: what changes when the block goes into a chip? Home: Active and passive in delivery. Practise: concept round.
How do you build a reactive slave agent? Home: Reactive slave agents. Practise: concept round.
How does a pipelined driver route out-of-order responses back? Home: Pipelined and out-of-order drivers. Practise: concept round.
Reset in the middle of a test: what must each component do? Home: Reset on the fly. Practise: concept round.
Why sample through a clocking block? What race does it prevent? Home: Monitor sampling, races and X. Practise: concept round.
How do you verify interrupts at block and at SoC level? Home: Interrupt agents.
Design a scoreboard: what do you predict from, and why not from the sequence? Home: Expected vs actual. Practise: Coding round, drill 1.
How do you build a scoreboard for AXI with outstanding, out-of-order transactions? Home: A queue per ID. Practise: Architecture round, scenario B.
What must be empty before a test may pass? Home: End-of-test checks. Practise: Debug round, log 2.
Where does the reference model live? When would you use DPI-C? Home: Predictor design. Practise: concept round.
Two checkers agree. How do you know either can fail? Home: The class-comparator trap. Practise: Debug round, log 4.
How do you check traffic that drops, reorders, splits or merges? Home: Scoreboards for messy traffic.
Build a coverage model from a spec. Where do you sample? Home: Designing a coverage model.
illegal_bins versus ignore_bins: when is an illegal bin wrong? Home: Bins, illegal bins and ignore bins. Practise: Behavioural, failure story.
Coverage is stuck. How do you close the last holes? Home: Closing coverage. Practise: Closure questions.
Coverage is 100%. Are you done? Home: Fault injection. Practise: Closure questions.
Code coverage versus functional coverage; who reviews exclusions? Home: Code coverage. Practise: Closure questions.
A cross has ten thousand bins. What do you do? Home: Crosses and plan traceability.
SVA cover property or covergroup? Home: SVA cover vs covergroups.
Desired versus mirrored value: when does each change? Home: Why a register model. Practise: concept round.
What is the adapter contract? What does provides_responses mean? Home: The adapter contract. Practise: Coding round, drill 4.
Auto versus explicit prediction: which and why? Home: Prediction modes. Practise: Debug round, log 5.
Why are volatile fields never compared by mirror(UVM_CHECK)? Home: Volatile fields and mirror checks. Practise: concept round.
Which built-in register sequences do you run, and how do you exclude registers? Home: Built-in sequences and NO_* attributes. Practise: concept round.
Backdoor access: how does it work, and what does peek do to the mirror? Home: Backdoor access. Practise: Debug round, log 5.
How does the register model scale to an SoC? Home: The register model at SoC scale. Practise: RAL interview set.
Walk me through debugging a hang. Home: Hang playbook. Practise: Debug round, log 1.
How can a test pass while checking nothing? How do you prevent it? Home: False-pass playbook. Practise: Debug round, log 2.
One scoreboard mismatch: how do you get to a minimal reproducer? Home: Mismatch playbook. Practise: Debug round, log 3.
You added one agent and different seeds now fail. Why? Home: Random stability and seeds.
A hundred failures overnight. How do you triage? Home: Regression triage by signature. Practise: Closure questions.
Where do you print a PASS/FAIL line that survives a fatal? Home: Report server and the verdict line.
How do you waive a known error without hiding new ones? Home: Report catchers and waivers. Practise: Closure questions.
Where do assertions belong: interface, bind file or the RTL? Who owns them? Home: Where assertions live.
An error-injection test trips your protocol assertion. How does the test switch one rule off without hiding real failures? Home: Assertion control from the test.
An assertion passed in every test. How do you know it was ever exercised (vacuous passes)? Home: Cover properties and closure.
Can the same properties run in formal? What changes between assert and assume? Home: Reusing properties in formal.
How does an assertion failure reach the UVM verdict and the regression triage? Home: Reporting assertion failures.
Take a block bench up to a subsystem. What changes? Home: Vertical reuse. Practise: Architecture round, scenario A.
Design the verification for an AXI interconnect or a cache controller. Home: Subsystem and SoC composition. Practise: Architecture round.
Buy or build VIP? How do you qualify bought VIP? Home: Integrating third-party VIP.
How do you split work between formal and simulation for a block? Home: Formal alongside simulation. Practise: Architecture round, scenario C.
What does gate-level simulation catch, and how do you run a UVM bench on a netlist? Home: Gate-level simulation.
What do you check in low-power verification? Home: Power-aware simulation.
How do you know you are done? Give numbers. Home: Metrics and sign-off. Practise: Closure questions.
What differs between UVM 1.2 and IEEE 1800.2 in practice? Home: The delta table.
What is the hardest bug you have found? Home: Telling your bug story. Practise: Behavioural round.
Tell me about a disagreement with a designer. Home: Behavioural round.
Tell me about a mistake you made and what changed afterwards. Home: Behavioural round.
How long would it take to verify this block? What if the schedule is cut by 30%? Home: Estimation and scheduling. Practise: Closure questions.
How do you bring a junior engineer up to speed? Home: Behavioural round.
So the answer you revise is the authoritative one. The course gives every fact one home; other pages link to it. Revising from the home lesson avoids learning a simplified version from a page where the fact was only mentioned.
Next: put the questions in the order a loop asks them. The Senior DV Interview Loop.