Interview Q&A: Full Checking Pipeline

[INT][SENIOR][UVM] MODEL ANSWER

Q: Full checking pipeline?

A:
  MECHANISM:  stim (seq→drv) → DUT → mon.ap fans to scb.act, cov, reg_predictor;
              ref_model generates scb.exp; RAL mirror.check at end; SVA on vif parallel.
  MOTIVATION:  Each layer checks different concern — no single component covers all.
  WHEN:       Complex block: combine RAL + scb + func cov + assertions per plan section.
  PITFALL:    Only scb OR only RAL — gaps in register vs datapath checking.
  EXAMPLE:    Narrate whiteboard: DMA block uses RAL for prog, scb for memory, cov on mon.ap.

[INT][SENIOR][UVM] MODEL ANSWER

Q: Block vs chip checking?

A:
  MECHANISM:  Block: local scb + block cov + RAL. Chip: end-to-end scb across subtrees,
              merged cov from block+chip runs, passive monitors on integrated interfaces.
  MOTIVATION:  Chip checks system scenarios block TB cannot see — integration is new evidence.
  WHEN:       Reuse block agents passive; add chip scoreboard path CPU→fabric→peripheral.
  PITFALL:    Chip TB only checks local block monitors — misses system routing bugs.
  EXAMPLE:    Block AES scb local; chip scb compares CPU plaintext injection to memory ciphertext.

[INT][SENIOR][UVM] MODEL ANSWER

Q: SVA vs scoreboard?

A:
  MECHANISM:  SVA: temporal protocol and safety properties on signals, always-on.
              Scoreboard: transaction-level functional compare, scenario-aware.
  MOTIVATION:  SVA catches immediate protocol violations; scb checks end-to-end data correctness.
  WHEN:       SVA on VIP interface for valid/ready rules; scb for packet content/memory result.
  PITFALL:    Replacing scb with SVA for algorithmic output check — SVA wrong abstraction.
  EXAMPLE:    SVA: awvalid stable until awready. Scb: ciphertext matches golden model.

[INT][SENIOR][UVM] full pipeline whiteboard

  [STIM] seq → drv → DUT
              │
              ▼
  [MON] mon.ap ──┬──► scb.act_imp
                 ├──► cov_sub (func bins)
                 ├──► reg_predictor → mirror
                 └──► ref_model input
                          │
                          ▼
                      scb.exp_imp

  [SVA] parallel on vif — protocol timing
  [RAL] mirror.check() in report/check phase

[INT][SENIOR][UVM] MODEL ANSWER

Q: report_phase checking summary?

A:
  MECHANISM:  Scoreboard prints match/mismatch counts; cov subscriber reports bin hit summary;
              regmodel.mirror(UVM_CHECK) or explicit field checks; test reviews UVM_ERROR count.
  MOTIVATION:  Final audit before test passes — drain and mirror catch silent gaps.
  WHEN:       report_phase or check_phase for scb drain; end of test mirror.check().
  PITFALL:    Test passes with UVM_ERROR if error limit raised — check counts explicitly.
  EXAMPLE:    scb.report: matched 10K, 0 exp left, 0 act left; mirror.check zero mismatches.

[INT][SENIOR][UVM] MODEL ANSWER

Q: Checking failure triage?

A:
  MECHANISM:  Bucket: scb mismatch, mirror.check fail, cov assertion, SVA fail, UVM_ERROR flood.
  MOTIVATION:  Bucket determines owner — scb team vs RAL team vs VIP protocol team.
  STEPS:      1) Manifest test+seed. 2) First UVM_ERROR message. 3) Repro seed locally.
              4) Classify bucket. 5) Assign owner. 6) Block merge if P0 closure test broken.
  PITFALL:    Re-run full farm without local repro — wastes time.
  EXAMPLE:    axi_rand seed 4099 mirror.check fail → RAL adapter bug, not DUT.

[INT][SENIOR][UVM] MODEL ANSWER

Q: Whiteboard AES block checking?

A:
  MECHANISM:  RAL for key/control registers. Ref model predictor on plaintext input txn.
              Output monitor → scb.act. Cov on mode×key_len cross from output mon.
              SVA on valid/ready at AES interface.
  MOTIVATION:  Interview tests you assign tools to concerns — not one mega-checker.
  PLAN:       Draw pipeline; label each box; state what failure each catches.
  PITFALL:    "Scoreboard checks everything" — misses RAL for key reg programming verification.
  EXAMPLE:    Key reg wrong via RAL check; algorithm wrong via scb; mode hole via func cov cross.

[INT][SENIOR][UVM] MODEL ANSWER

Q: False failures from monitor?

A:
  MECHANISM:  Wrong sample point → scb mismatch and cov wrong bins simultaneously.
  MOTIVATION:  If scb and cov disagree with waves, suspect monitor before DUT/ref model.
  WHEN:       First mismatch in bring-up — verify mon txn against wave before blaming DUT.
  PITFALL:    Weeks debugging ref model when monitor samples setup phase not complete transfer.
  EXAMPLE:    APB mon fixed to sample penable&&pready — scb mismatches drop from 100% to 0.

[INT][SENIOR][UVM] MODEL ANSWER

Q: Smoke test checking trim?

A:
  MECHANISM:  Smoke: basic scb or directed compare + critical SVA; disable heavy cov merge;
              optional skip mirror.check for speed — but document smoke is not sign-off.
  MOTIVATION:  Farm economics — smoke proves bring-up; closure runs full pipeline.
  WHEN:       Every commit smoke 30min; nightly full merge with all checks enabled.
  PITFALL:    Signing off block on smoke config with cov disabled — process failure not TB choice.
  EXAMPLE:    Smoke: directed 10 txns + scb; nightly: rand + full cov + mirror.check + merge.