Part 11 · Senior Prep · Intermediate

Interview Q&A: Predictor Patterns

Model answers on uvm_reg_predictor, bus2reg mapping, ref model predictors for scoreboard, side-effect modeling, and shared monitor streams.

RAL predictor

Q: What does uvm_reg_predictor do?

diagram

[INT][SENIOR][UVM] MODEL ANSWER

Q: uvm_reg_predictor?

A:
  MECHANISM:  Subscribes to bus monitor txn stream; adapter bus2reg converts to reg bus op;
              calls map.predict() to update mirrored register values.
  MOTIVATION:  Mirror tracks all bus-visible register activity — including external masters.
  WHEN:       Any multi-master map or when auto_predict insufficient; always with frontdoor traffic.
  PITFALL:    Predictor not connected to mon.ap — mirror stale after RTL/DMA writes reg.
  EXAMPLE:    env.connect: mon.ap → reg_predictor.bus_in; reg_predictor.map = regmodel.default_map.

Q: bus2reg vs reg2bus — must they match?

diagram

[INT][SENIOR][UVM] MODEL ANSWER

Q: bus2reg vs reg2bus consistency?

A:
  MECHANISM:  reg2bus encodes register access as bus txn for driver; bus2reg decodes
              monitor txn back to reg operation for predict — semantic inverse pair.
  MOTIVATION:  Mismatch causes predictor to update wrong register/field on observed traffic.
  WHEN:       Same adapter class implements both — verify with loopback test.
  PITFALL:    Byte lane mapping differs between directions — intermittent mirror corruption.
  EXAMPLE:    Sub-word APB write: reg2bus sets pstrb; bus2reg reads pstrb to update correct byte field.

Q: How do you model register side effects in predictor?

diagram

[INT][SENIOR][UVM] MODEL ANSWER

Q: Side effects in predictor?

A:
  MECHANISM:  Custom predict hook or reg callback — writing CTRL.START sets STATUS.BUSY
              in mirror even if STATUS not on bus this cycle.
  MOTIVATION:  RTL updates shadow/status fields without bus readback — mirror must model spec.
  WHEN:       Sticky bits, auto-clear, linked fields — beyond plain bus decode.
  PITFALL:    Plain bus2reg only — misses HW side effect, mirror.check fails on STATUS.
  EXAMPLE:    CTRL.KICK write → callback sets STATUS.RUNNING in mirror per spec section 4.2.

diagram

[INT][SENIOR][UVM] RAL predictor wiring (whiteboard)

  mon.ap → reg_predictor.bus_in
  reg_predictor.adapter = axi_reg_adapter
  reg_predictor.map = regmodel.default_map
       │
       ▼
  bus2reg → map.predict() → mirror update

Key takeaways

reg_predictor connects monitor to mirror via bus2reg.
reg2bus and bus2reg must be semantic inverses.
Side effects need callbacks — plain decode insufficient.

Common pitfalls

Predictor disconnected — #1 mirror drift with external masters.
Ignoring W1C in bus2reg predict path.

Ref model and shared streams

Q: Ref model predictor for scoreboard — pattern?

diagram

[INT][SENIOR][UVM] MODEL ANSWER

Q: Ref model predictor pattern?

A:
  MECHANISM:  Input txn from mon.ap → ref_model.predict() → expected output txn → scb.exp_imp.
  MOTIVATION:  Expected stream generated from spec model, not from DUT observation.
  WHEN:       Algorithmic blocks: crypto, DMA transform, packet parser.
  PITFALL:    Ref model fed from driver stream — expected before DUT actually saw input.
  EXAMPLE:    encrypt_mon → ref_model.predict plaintext → scb.exp; output_mon → scb.act.

Q: Can one monitor stream feed scb, cov, and predictor?

diagram

[INT][SENIOR][UVM] MODEL ANSWER

Q: Shared monitor stream?

A:
  MECHANISM:  analysis_port fan-out — mon.ap connects to multiple analysis_export/imps.
  MOTIVATION:  One DUT-visible observation point — checking, coverage, RAL all consistent.
  WHEN:       Standard env connect: scb.act, cov_sub, reg_predictor all on agt.ap.
  PITFALL:    Separate monitors on same bus at different sample points — inconsistent views.
  EXAMPLE:    agt.ap → scb.act_imp + axi_cov.analysis_export + reg_pred.bus_in.

Q: Predictor vs scoreboard — different roles?

diagram

[INT][SENIOR][UVM] MODEL ANSWER

Q: Predictor vs scoreboard?

A:
  MECHANISM:  reg_predictor updates RAL mirror state; ref_model predictor generates
              expected txn for scoreboard compare — different consumers and goals.
  MOTIVATION:  RAL predictor = register state tracking; ref predictor = datapath expected stream.
  WHEN:       Both may share mon.ap but write to different downstream state (mirror vs exp_q).
  PITFALL:    Using reg_predictor output as scoreboard expected for algorithmic output — wrong layer.
  EXAMPLE:    mon.ap → reg_pred (mirror update) AND → ref_model → scb.exp (ciphertext expected).

Q: How do you debug predictor updating wrong register?

diagram

[INT][SENIOR][UVM] MODEL ANSWER

Q: Wrong register in predictor?

A:
  MECHANISM:  bus2reg returns wrong addr/field mapping — mirror updates wrong reg.
  STEPS:      1) Log bus2reg output addr/data per txn. 2) Compare to RTL decode table.
              3) Verify offset math in adapter. 4) Check byte enable on sub-word writes.
  PITFALL:    Fixing mirror.check expected value instead of fixing adapter mapping.
  EXAMPLE:    32-bit map on 64-bit bus — bus2reg uses wrong strobe lane, STATUS byte wrong.