Interview Q&A: Functional Coverage

[INT][SENIOR][UVM] MODEL ANSWER

Q: Coverage on monitor?

A:
  MECHANISM:  Subscriber on mon.ap samples covergroup when DUT-visible txn completes.
  MOTIVATION:  Coverage answers 'was scenario exercised?' — must reflect DUT reality, not intent.
  WHEN:       Always sample on monitor stream; never on driver pre-drive stream alone.
  PITFALL:    Driver-sampled bins green while DUT never saw error response — closure escape.
  EXAMPLE:    axi_cov samples resp_type on mon.ap after handshake — includes slverr from DUT.

[INT][SENIOR][UVM] MODEL ANSWER

Q: Functional vs code coverage?

A:
  MECHANISM:  Code coverage = which RTL lines toggled. Functional = which scenario bins hit
              per verification plan (crosses, error modes, config combos).
  MOTIVATION:  Code coverage necessary not sufficient — can hit all lines without key crosses.
  WHEN:       Sign-off uses plan-mapped functional coverage merge; code cov supporting metric.
  PITFALL:    Quoting 95% line coverage as 'done' — interview red flag for senior role.
  EXAMPLE:    All lines hit but interrupt_storm cross never sampled — func hole remains.

[INT][SENIOR][UVM] MODEL ANSWER

Q: Coverage subscriber?

A:
  MECHANISM:  uvm_subscriber #(txn) with write() calling cg.sample() from txn fields;
              connected to mon.ap via analysis_export in connect_phase.
  MOTIVATION:  Keeps covergroups out of monitor — separation of observe vs measure.
  WHEN:       Per-protocol cov subscriber; enable/disable via cfg for sim speed.
  PITFALL:    Covergroup inside driver — samples intent not DUT-visible outcome.
  EXAMPLE:    axi_cov_sub extends uvm_subscriber#(axi_txn); write(t) cg.sample(t).

[INT][SENIOR][UVM] coverage vs checking (whiteboard)

  mon.ap ──┬──► scoreboard.act_imp   (CORRECT? — checking)
           └──► axi_cov_sub.write()  (EXERCISED? — coverage)

  Different questions — parallel paths from same monitor

[INT][SENIOR][UVM] MODEL ANSWER

Q: Cross coverage?

A:
  MECHANISM:  covergroup cross(bin_a, bin_b) tracks combined scenario corners.
  MOTIVATION:  Individual bins may hit but critical combo missed — cross finds holes.
  WHEN:       Plan-defined combos: burst_len × resp_type, cfg_mode × error_inject.
  PITFALL:    Unconstrained cross explosion — 50×50 cross impractical, needs bin ignore/merge.
  EXAMPLE:    cross write_len, slverr — ensures long write WITH error response seen together.

[INT][SENIOR][UVM] MODEL ANSWER

Q: Coverage merge?

A:
  MECHANISM:  Simulation writes coverage database; merge tool unions bins across tests/seeds
              into project view mapped to verification plan sections.
  MOTIVATION:  No single test hits all bins — closure is merge evidence across regression.
  WHEN:       Nightly merge against plan; block + chip views combined for IP reuse credit.
  PITFALL:    Declaring hole closed from one lucky seed — merge proves reachability across seeds.
  EXAMPLE:    Block AXI 92% + chip integration adds 6% on system crosses → merged 98%.

[INT][SENIOR][UVM] MODEL ANSWER

Q: Coverage done answer?

A:
  MECHANISM:  Done = plan compliance — merged func cov by section, P0 holes closed
              or waived with audit, trend improving, not single metric threshold alone.
  MOTIVATION:  'Done' is evidence package — not a feeling or one number.
  ANSWER:     Show merged func cov %, enumerate open P0 holes + closure plan, waiver list.
  PITFALL:    '98% coverage' without naming which plan section or which P0 hole remains.
  EXAMPLE:    "AXI 98% plan, 1 P0 cross (irq_storm×reset) closure test lands Wed, 2 waivers approved."

[INT][SENIOR][UVM] MODEL ANSWER

Q: Close coverage hole?

A:
  MECHANISM:  Reproduce unreachable bin: directed seq, constraint tweak, config change,
              or prove unreachable with spec cite → formal waiver path.
  MOTIVATION:  Data beats opinion — directed reproducer before waiver request.
  WHEN:       P0 hole from merge report — owner assigned, closure test in regression within SLA.
  PITFALL:    Waiver without repro attempt or spec cite — audit failure at tape-out review.
  EXAMPLE:    slverr×4K cross hole → axi_err_seq directed + cfg addr aligned → bin hits.