Interview Q&A: RAL Mirror & Predict

[INT][SENIOR][UVM] MODEL ANSWER

Q: Mirror vs predict?

A:
  MECHANISM:  Mirror is RAL model's belief of DUT register state. Predict updates
              mirror — via auto_predict or uvm_reg_predictor from observed bus traffic.
  MOTIVATION:  Tests read mirror for expected value; compare against spec without
              manual shadow variables in sequences.
  WHEN:       auto_predict=1 for simple maps; separate predictor when bus encoding
              ≠ flat register image (side effects, aliases, external masters).
  PITFALL:    mirror.check() fails because predictor not wired — mirror stale.
  EXAMPLE:    SW write via frontdoor → mon → predictor → mirror update →
              seq mirror.read(status, val) matches DUT.

[INT][SENIOR][UVM] MODEL ANSWER

Q: Desired vs mirrored?

A:
  MECHANISM:  Desired = intended value after set()/update(). Mirrored = believed
              current DUT state — updated by predict, write, read, or reset.
  MOTIVATION:  set()+update() stages SW intent; mirror tracks what DUT actually holds.
  WHEN:       set before update/write; get_mirrored_value() for check; get() for desired.
  PITFALL:    Comparing desired to DUT and calling it mirror check — wrong value view.
  EXAMPLE:    reg.set(0xFF); reg.update(); write pushes to DUT; predict refreshes mirror from bus.

[INT][SENIOR][UVM] MODEL ANSWER

Q: set / update / write / read?

A:
  MECHANISM:  set() changes desired only (no bus). update() pushes desired→DUT delta.
              write() sets desired and pushes. read() bus read refreshes mirror from DUT.
  MOTIVATION:  Batch SW programming: multiple set() then one update() — efficient bursts.
  WHEN:       set+update for SW-like staging; write for single-shot; read after DUT may change reg.
  PITFALL:    set() expecting DUT change — no bus cycle until update/write.
  EXAMPLE:    prog_seq: ctrl.set(EN); mask.set(ALL); ctrl.update(); mask.update();

[INT][SENIOR][UVM] two-value model (whiteboard)

  DESIRED  (intent)     set() / write() first half
  MIRRORED (belief)     predict / read / reset / auto_predict after bus

  mirror(UVM_CHECK) compares MIRRORED vs backdoor peek of DUT flop

[INT][SENIOR][UVM] MODEL ANSWER

Q: auto_predict vs explicit predictor?

A:
  MECHANISM:  auto_predict=1: RAL updates mirror on frontdoor ops automatically.
              Explicit predictor: monitor txn → bus2reg → reg.predict(data) for all bus traffic.
  MOTIVATION:  auto_predict misses traffic from external masters or side-effect fields;
              predictor sees every observed bus write/read.
  WHEN:       auto_predict for single-master simple map; predictor when DUT/RTL also writes regs.
  PITFALL:    auto_predict with second bus master — mirror diverges silently until check fails.
  EXAMPLE:    DMA engine writes descriptor reg — only predictor path updates mirror correctly.

[INT][SENIOR][UVM] MODEL ANSWER

Q: RAL mirror mismatch debug?

A:
  MECHANISM:  mirror.check() compares mirror to backdoor peek of DUT register flop.
  MOTIVATION:  Catches predictor bugs, reset value errors, field width/endian mistakes.
  STEPS:      1) Predictor connected to mon.ap? 2) regmodel.reset() after reset deassert?
              3) Field policy W1C/RC modeled? 4) Adapter byte order correct?
              5) auto_predict conflicting with predictor?
  PITFALL:    mirror.check() before reset deassert — reset value noise.
  EXAMPLE:    STATUS W1C bit — predictor must model write-1-to-clear, not plain overwrite.

[INT][SENIOR][UVM] MODEL ANSWER

Q: RAL field policies?

A:
  MECHANISM:  RO (read-only), WO, RW, W1C (write-1-clear), RC (read-clears), volatile.
  MOTIVATION:  Predictor and mirror must model spec semantics — not all fields are RW.
  WHEN:       W1C status bits, RC interrupt flags, RO version ID — each differs in predict.
  PITFALL:    Plain write predict on W1C — mirror wrong after clear operation.
  EXAMPLE:    INT_STATUS W1C: write 0x4 clears bit 2; predict clears bit, not OR-in 0x4.

[INT][SENIOR][UVM] MODEL ANSWER

Q: mirror.check vs read compare?

A:
  MECHANISM:  mirror(UVM_CHECK) backdoor-peeks DUT and compares to mirrored in one call.
              read() performs frontdoor bus cycle and updates mirror from bus result.
  MOTIVATION:  check validates model tracking; read validates bus path + DUT response.
  WHEN:       End of test integrity audit: mirror.check(). Mid-test: read() for live bus proof.
  PITFALL:    Only mirror.check() in test that never exercised frontdoor — no bus proof.
  EXAMPLE:    After prog sequence: read(STATUS) frontdoor; end of test: regmodel.mirror(UVM_CHECK).