Interview Q&A: Scoreboard Architecture

[INT][SENIOR][UVM] MODEL ANSWER

Q: Scoreboard mechanism?

A:
  MECHANISM:  Two analysis imps (expected + actual) receive txn streams; match engine
              pairs them; UVM_ERROR on mismatch; match_count++ on success.
  MOTIVATION:  Automates self-checking — test cannot pass with broken DUT silently.
  WHEN:       Any block with transform or request/response checking requirement.
  NOT WHEN:   Pure register block with no datapath — RAL may suffice alone.
  PITFALL:    Single stream compare — no expected source defined — checks nothing meaningful.
  EXAMPLE:    AES scb: ref_model exp on encrypt req; DUT mon act on ciphertext output.

[INT][SENIOR][UVM] MODEL ANSWER

Q: Expected stream sources?

A:
  MECHANISM:  Three sources: (1) reference model predict from input txn, (2) golden
              monitor on known-good path, (3) transformed copy of stimulus txn.
  MOTIVATION:  Expected must be independent of DUT broken behavior — not DUT copy.
  WHEN:       Ref model for algorithmic blocks; golden VIP for protocol stack compare.
  PITFALL:    Expected = copy of actual with delay — checks nothing, always passes.
  EXAMPLE:    DMA scb: ref_model predicts memory contents; act from memory monitor on DUT port.

[INT][SENIOR][UVM] MODEL ANSWER

Q: Dual analysis imps?

A:
  MECHANISM:  uvm_analysis_imp_decl(_exp) and (_act) create write_exp/write_act
              callbacks — separate queues per stream.
  MOTIVATION:  Type-safe handling; independent queue depth tracking; clear ownership.
  WHEN:       Standard scoreboard pattern — always dual imp for two-stream compare.
  PITFALL:    One write() demux by txn flag — works but loses queue diagnostics clarity.
  EXAMPLE:    scb: exp_q.push(write_exp clone); act_q.push(write_act clone); try_match().

[INT][SENIOR][UVM] scoreboard pipeline (whiteboard)

  stim → DUT → [MON act] → scb.act_imp
  stim → ref_model → [EXP txn] → scb.exp_imp
              ↓
         match engine → MATCH / UVM_ERROR

[INT][SENIOR][UVM] MODEL ANSWER

Q: FIFO vs ID matching?

A:
  MECHANISM:  FIFO: strict in-order pop exp and act queues — O(1), fragile to reorder.
              ID map: associative array keyed by txn ID — handles out-of-order completion.
  MOTIVATION:  Protocol determines matcher — APB in-order OK with FIFO; AXI needs ID map.
  WHEN:       FIFO for APB/SRAM strict order; ID map for AXI/PCIe with reordering.
  PITFALL:    FIFO on reordering bus — false mismatch when DUT returns responses out of order.
  EXAMPLE:    AXI scb: pending[txn.id] stores exp; act arrives with id → lookup compare.

[INT][SENIOR][UVM] MODEL ANSWER

Q: check_phase drain?

A:
  MECHANISM:  check_phase reports unmatched exp or act queue leftovers — silent drops
              become UVM_ERROR or warning with counts.
  MOTIVATION:  Test can pass with 0 mismatches but missing responses — drain catches this.
  WHEN:       Every scoreboard implements check_phase summary: exp_left, act_left, match_count.
  PITFALL:    No drain — test passes, 500 expected txns never arrived from DUT.
  EXAMPLE:    check_phase: if (exp_q.size()) uvm_error("DRAIN", $sformatf("%0d exp unmatched", exp_q.size())).

[INT][SENIOR][UVM] MODEL ANSWER

Q: Scoreboard mismatch debug?

A:
  MECHANISM:  Mismatch = paired exp/act differ OR matcher cannot pair — classify which.
  STEPS:      1) First mismatch txn dump side-by-side. 2) Queue depths — one-sided stall?
              3) Ref model input correct? 4) Monitor sample point? 5) Endian/width?
              5) Reorder: wrong matcher type?
  PITFALL:    Fixing DUT when ref model bug — always verify exp independently first.
  EXAMPLE:    exp_q depth 100, act_q depth 0 — DUT mon silent, not compare logic bug.

[INT][SENIOR][UVM] MODEL ANSWER

Q: Scoreboard vs RAL?

A:
  MECHANISM:  RAL models register map state; scoreboard compares transaction streams
              (datapath algorithmic results, packet contents, memory arrays).
  MOTIVATION:  Registers and datapath have different checking needs — complementary.
  WHEN:       RAL for programming sequence; scb for AES output, DMA memory, packet payload.
  PITFALL:    RAL mirror as only checker for crypto block output — wrong abstraction level.
  EXAMPLE:    AES: RAL checks key reg write; scb checks ciphertext vs golden ref model.