Part 11 · Senior Prep · Intermediate
Interview Q&A: Frontdoor & Backdoor Access
Model answers on reg adapter, frontdoor bus path, backdoor HDL access, uvm_hdl_deposit, and sign-off implications of each access type.
Access path fundamentals
Q: Frontdoor vs backdoor?
diagram
[INT][SENIOR][UVM] MODEL ANSWER
Q: Frontdoor vs backdoor?
A:
MECHANISM: Frontdoor uses bus adapter (real APB/AXI path through sequencer/driver).
Backdoor uses uvm_hdl_deposit/read on RTL hierarchy — bypasses bus.
MOTIVATION: Frontdoor proves integration; backdoor sets state fast or injects corners.
WHEN: Frontdoor for normal tests and SW-like sequences; backdoor for preload,
fault injection, debug shortcuts not reachable via bus.
NOT WHEN: Signing off bus protocol with only backdoor writes — no path proof.
PITFALL: Backdoor write while frontdoor traffic in flight — mirror/DUT diverge.
EXAMPLE: reg.write(CFG, val, UVM_FRONTDOOR) via adapter; SRAM preload via backdoor pre_main.Q: Explain the RAL frontdoor path end-to-end
diagram
[INT][SENIOR][UVM] MODEL ANSWER
Q: Frontdoor path end-to-end?
A:
MECHANISM: reg.write → map → adapter.reg2bus → bus txn → sequencer → driver → DUT.
Return path: DUT → monitor → predictor.bus2reg → predict() → mirror update.
MOTIVATION: Exercises real bus protocol, address decode, byte enables, wait states.
WHEN: Default for register programming sequences mimicking firmware.
PITFALL: Adapter reg2bus wrong byte order — writes succeed on bus but wrong register field.
EXAMPLE: APB adapter maps reg offset to paddr; driver drives APB; mon feeds predictor.Q: What is the reg adapter's job?
diagram
[INT][SENIOR][UVM] MODEL ANSWER
Q: Reg adapter role?
A:
MECHANISM: Extends uvm_reg_adapter — reg2bus converts reg access to bus txn;
bus2reg converts monitored bus txn back to reg update for predictor.
MOTIVATION: Decouples RAL map from bus protocol — swap adapter for AXI vs APB same regmodel.
WHEN: Every frontdoor RAL integration — adapter connects reg model to agent bus txn type.
PITFALL: bus2reg not inverse of reg2bus — predictor updates wrong fields.
EXAMPLE: axi_reg_adapter: reg2bus packs awaddr/awdata; bus2reg unpacks monitor txn to reg.diagram
[INT][SENIOR][UVM] RAL paths (whiteboard)
FRONTDOOR:
seq → reg.write/read → adapter → bus → DUT
DUT → mon → predictor → mirror
BACKDOOR:
seq → reg.write(..., UVM_BACKDOOR) → uvm_hdl_deposit → DUT flop
(no bus cycle — fast, no protocol check)Key takeaways
Frontdoor = bus path + adapter + predictor; proves integration.
Backdoor = HDL peek/poke — fast setup, not bus sign-off evidence.
Adapter reg2bus and bus2reg must be consistent.
Common pitfalls
Backdoor preload during active bus traffic — race on mirror and DUT.
Sign-off with backdoor-only register tests — escaped bus integration bugs.
Backdoor usage and HDL paths
Q: When is backdoor access appropriate?
diagram
[INT][SENIOR][UVM] MODEL ANSWER
Q: When backdoor appropriate?
A:
MECHANISM: uvm_hdl_deposit/read on reg backdoor path — direct RTL signal access.
MOTIVATION: Speed for RAM preload, internal flop injection, unreachable scan paths.
WHEN: pre_main memory init; inject fault in internal state; debug when bus broken.
NOT WHEN: Normal programming sequence sign-off; protocol compliance evidence.
PITFALL: Backdoor changes not visible to monitor — predictor won't update unless manual predict.
EXAMPLE: Backdoor preload SRAM; run frontdoor-only traffic test; scb checks datapath.Q: How do you configure backdoor paths in RAL?
diagram
[INT][SENIOR][UVM] MODEL ANSWER
Q: Backdoor path configuration?
A:
MECHANISM: regmodel.build: set_hdl_path or add_hdl_path on reg/block linking
to RTL hierarchy string; backdoor ops use uvm_hdl_deposit on that path.
MOTIVATION: Generator or manual bind ties RAL register to specific flop path.
WHEN: build() after regmodel instantiation; verify with peek after reset.
PITFALL: HDL path typo — backdoor silently fails or writes wrong hierarchy.
EXAMPLE: ctrl_reg.add_hdl_path("dut.u_reg_block.ctrl_reg"); peek matches reset spec.Q: Backdoor write — does mirror auto-update?
diagram
[INT][SENIOR][UVM] MODEL ANSWER
Q: Backdoor mirror update?
A:
MECHANISM: reg.write(..., UVM_BACKDOOR) updates mirror by default after successful deposit.
Predictor does not see backdoor — no bus txn on monitor stream.
MOTIVATION: Mirror stays consistent for subsequent mirror.check() after backdoor setup.
WHEN: Preload then frontdoor traffic — mirror reflects preload until bus overwrites.
PITFALL: Manual uvm_hdl_deposit bypassing reg API — mirror stale, check fails later.
EXAMPLE: reg.write(MEM[0], 32'hDEAD, UVM_BACKDOOR); mirror updated; frontdoor read confirms.Q: Can you mix frontdoor and backdoor in one test?
diagram
[INT][SENIOR][UVM] MODEL ANSWER
Q: Mix frontdoor and backdoor?
A:
MECHANISM: Common pattern: backdoor preload in pre_main/pre_configure; frontdoor
runtime traffic; end mirror.check() validates final state.
MOTIVATION: Fast setup + realistic runtime exercise — best of both when documented.
WHEN: Memory init backdoor; all register programming frontdoor; plan documents split.
PITFALL: Concurrent backdoor poke during frontdoor reg traffic — race and mirror corruption.
EXAMPLE: backdoor SRAM fill; frontdoor DMA kick-off; scb checks output; mirror.check() end.systemverilog
// adapter skeleton — interview whiteboard expectation
class axi_reg_adapter extends uvm_reg_adapter;
function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw);
axi_txn t = axi_txn::type_id::create("t");
t.addr = rw.addr; t.data = rw.data; t.write = (rw.kind == UVM_WRITE);
return t;
endfunction
function void bus2reg(uvm_sequence_item bus_item, ref uvm_reg_bus_op rw);
// unpack monitor txn → rw for predictor
endfunction
endclassKey takeaways
Backdoor for fast setup/debug — not bus sign-off substitute.
HDL paths must be verified — typo = silent wrong write.
Use reg API for backdoor — keeps mirror consistent.
Common pitfalls
Raw uvm_hdl_deposit without reg.write — mirror drift.
Concurrent backdoor + frontdoor on same register — race.