DenseChip

Computer Architecture · All levels

Bottleneck Analysis Framework — Debug Playbook

Debug Playbook for Bottleneck Analysis Framework (Performance Analysis).

On-call / interview prompt

Bottleneck Analysis Framework looks wrong — walk your first five debug steps.

diagram
ARCHITECTURE ANALYSIS CHAIN

1. METRIC     — IPC, CPI, MPKI, bandwidth, latency, queue depth, stall cycles
2. HYPOTHESIS — microarch or system cause ordered by likelihood
3. EXPERIMENT — trace, PMU counter, simulation, or RTL probe
4. CHANGE      — pipeline, cache, NoC, or memory hierarchy adjustment
5. VALIDATION  — workload replay, regression suite, PPA impact

Reference workflow

diagram
1. Confirm workload, model tag, seed, and PMU/counter definitions
2. Open the primary report and capture worst metric
3. Correlate metric with workload phase, structure, traffic class, or RTL hierarchy
4. Apply smallest fix with documented hypothesis
5. Re-run required workload, PPA, and verification regressions

Mechanism to narrate

  • Separate symptom from root cause

  • Fix systematic clusters before one-offs

Common pitfalls

  • Random optimization without metric

  • Skipping regression after local fix

Staff-level debug discipline

For Bottleneck Analysis Framework, senior debug is branch-and-bound: reduce the search space quickly, keep experiments reversible, and avoid hiding a systematic issue behind one local fix.

Debug decision tree

  1. Reproduce the failure with the same workload, model tag, seed, and counter setup.

  2. Classify the failure as workload issue, model issue, microarchitecture issue, software issue, implementation issue, or true product limitation.

  3. Run one cheap experiment that can falsify the leading hypothesis.

  4. Prefer a fix that improves a cluster over one that only hides the worst line.

  5. After the fix, re-check Performance Analysis closure dashboard and the likely regression surface: Architecture spec updates and performance closure schedule..

Escalation triggers

  • The failure crosses architecture, RTL, verification, software, PD, or product ownership.

  • The proposed fix consumes area, power, latency, or verification margin needed elsewhere.

  • The issue repeats across workloads or blocks, suggesting methodology or model root cause.

  • The remaining risk is silicon-facing: Misidentifying bottlenecks creates local wins but global regressions..

Debug branch diagram

diagram
VISUAL MODEL — Performance Analysis / Bottleneck Analysis Framework

        workload / trace
              │
              ▼
   metric symptom (IPC, MPKI, bandwidth, latency, stalls)
              │
              ▼
     likely microarchitectural mechanism
              │
      ┌───────┼────────┐
      ▼       ▼        ▼
  pipeline  memory    fabric/coherency
  stalls    misses    queues / ordering
      │       │        │
      └───────┼────────┘
              ▼
        bounded design change
              │
              ▼
   validation workload + PPA regression

Tradeoff matrix

diagram
TRADEOFF MATRIX — Bottleneck Analysis Framework

+----------------------+----------------------+----------------------+----------------------+
| Option               | Helps                | Can hurt             | Validation needed    |
+----------------------+----------------------+----------------------+----------------------+
| Larger / wider block | peak perf, miss rate | area, power, timing  | workload sweep       |
| Smarter policy       | hit rate, QoS, IPC   | verification risk    | corner cases + PMU   |
| More buffering       | latency tails, stalls| deadlock, leakage    | stress traffic tests |
| Software contract    | locality, ordering   | portability, APIs    | production workload  |
+----------------------+----------------------+----------------------+----------------------+

Senior rule: pick the smallest change that proves or disproves the mechanism.

Architecture deep dive

PMU evidence beats intuition for architecture decisions.

Concept diagram

diagram
TOP-DOWN PERFORMANCE METHOD

Total cycles
 ├─ Retiring useful work
 ├─ Frontend bound
 ├─ Bad speculation
 ├─ Backend core bound
 └─ Backend memory bound

Only after classification should you propose cache, branch, pipeline, or NoC changes.

Metric graph

diagram
ROOFLINE SKETCH

Performance
  ^
  |                     compute roof
  |-------------------------------
  |                   /
  |                 /
  |               /   ● workload A (compute-bound)
  |             /
  |   ● workload B (memory-bound)
  +---------------------------------> arithmetic intensity
        memory bandwidth slope

Metrics and artifacts

  • PMU event sets

  • roofline chart

  • top-down stall breakdown

  • workload sensitivity matrix

Mini case study

Team proposed wider SIMD but roofline showed memory-bound kernel — bandwidth upgrade and locality fix delivered 2× speedup at lower area cost.

Debug branches

  • If counters disagree with sim, align workload and warmup.

  • If bottleneck unclear, use top-down method before microarch tweaks.

Senior review question

Ask: what single metric would prove this concept is working or failing on your workload?

Key takeaways

  • Connect every architecture claim to a workload and measurable metric.

  • State verification and PPA impact before proposing design changes.

Common pitfalls

  • Feature-driven design without MPKI/IPC/bandwidth evidence.

  • Ignoring coherency and NoC traffic in cache and accelerator sizing.

Study notes

Re-read this topic with one concrete workload.

Practice this lesson