START condition (SDA falls while SCL high) → 7-bit address + R/W bit → ACK from target → data bytes with ACK/NACK → STOP (SDA rises while SCL high). Each byte is 8 data bits plus ACK bit on the 9th clock.
Open-drain means a device pulls the line low or releases it; the pull-up returns the line high. Resistance and bus capacitance set rise time, while the low-level sink-current and VOL limits bound how strong the pull-up may be. Select the value from the required I²C mode, measured/estimated capacitance and every participant's electrical limits.
I2C READ TRANSACTION
START | ADDR+W | ACK | REG_ADDR | ACK | Sr | ADDR+R | ACK | DATA | NACK | STOP
S last byteDuring clock stretching, a target can hold SCL low after a controller releases it. A controller that supports stretching observes the actual SCL level before advancing. Any timeout and recovery action are system/controller policies; choose them from the target's documented maximum behaviour rather than assuming an I²C-wide limit.
With multiple controllers, arbitration is performed while SCL is high: a controller that releases SDA but observes it low has lost arbitration and stops driving the transfer as specified. Retry timing and software reporting belong to the controller/platform contract.
Fast mode (400 kHz) and Fast mode Plus (1 MHz) have tighter timing.
Address NACK candidates include no powered/ready target at that address, an address/strap mismatch, or electrical/timing failure; inspect the bus before choosing one.
Repeated START (Sr) for read-after-write without releasing bus.
Fast mode (400 kHz) and Fast mode Plus (1 MHz) have tighter timing.
Address NACK candidates include no powered/ready target at that address, an address/strap mismatch, or electrical/timing failure; inspect the bus before choosing one.
Repeated START (Sr) for read-after-write without releasing bus.