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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals25
  • AMBA Family (APB / AHB / AXI)17
  • Coherence Fabrics (ACE / CHI)17
  • Memory Interfaces (DDR / LPDDR / HBM)17
  • PCIe & CXL17
  • Embedded Peripherals (I2C / SPI / UART)17
    • I2C Timing & Arbitration
      • I2C Timing & Arbitration: Concepts
      • I2C Timing & Arbitration: Integration
      • I2C Timing & Arbitration: Debug
      • I2C Timing & Arbitration: Interview
    • SPI Modes & Chip-Select Rules
    • UART Flow Control
    • Peripheral Integration Debug
    • Embedded Peripherals (I2C / SPI / UART): Tricky Q&A
  • High-Speed I/O (USB / Ethernet / MIPI)17
  • Protocol Verification & Compliance17
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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←I2C Timing & Arbitration
  1. Topics
  2. Bus Protocols
  3. Embedded Peripherals (I2C / SPI / UART)
  4. I2C Timing & Arbitration
  5. I2C Timing & Arbitration: Integration

Interface ProtocolsAll levels

I2C Timing & Arbitration: Integration

Integration for I2C Timing & Arbitration.

Integration in practice

Board and firmware integration

Pull-up selection depends on bus capacitance, required rise time and participant sink capability. Added devices often add capacitance, but simply lowering resistance can violate low-level current or VOL limits; calculate and measure both bounds.

Firmware must match the target address (often influenced by strap pins), supported bus mode and register map. Two targets responding to the same address can both acknowledge; later read data or command interpretation may conflict rather than producing a reliable NACK.

  • Verify pull-ups on board schematic — missing pull-ups = no communication.

  • Reset sequence: device must be out of reset before I2C access.

  • Shared segment: ensure simultaneously enabled targets do not respond to the same address unless a mux, enable or other selection scheme isolates them.

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See also

  • I2C Timing & Arbitration: Interview