CPOL=0 means the clock idles low; CPOL=1 means it idles high. In the conventional four-mode naming, CPHA selects whether capture occurs on the first or second clock transition after chip select. Confirm the controller's terminology and the device timing diagram rather than relying only on a mode number.
Data shifts on one edge, samples on the opposite. MOSI (master out) and MISO (master in) shift simultaneously — full duplex. MSB or LSB first is device-specific.
SPI MODE 0 (CPOL=0, CPHA=0)
CS ‾‾‾\___________________________/‾‾‾
SCLK ___|‾|_|‾|_|‾|_|‾|_|‾|_|‾|___
MOSI [D7][D6][D5][D4][D3][D2][D1][D0]
sample on rising edgeCS must be active (low for active-low) before the first clock edge and remain active through the transfer. CS deassert too early = truncated transfer. Setup time between CS assert and first clock varies by device.
Some devices require CS high between transactions. Others allow back-to-back with CS held low. Flash devices often need specific CS timing for deep power-down entry/exit.
CS polarity: active-low is common but not universal.
Multi-slave: separate CS per device, shared CLK/MOSI/MISO.
SPI flash: command + address + dummy + data phases in one CS assertion.
CS polarity: active-low is common but not universal.
Multi-slave: separate CS per device, shared CLK/MOSI/MISO.
SPI flash: command + address + dummy + data phases in one CS assertion.