The memory controller translates AXI (or similar) requests into DRAM commands: ACTIVATE (open row), READ, WRITE, PRECHARGE (close row), REFRESH. Scheduling policy determines which pending request gets the next command slot.
Row buffer (page) policy: open-page keeps a row active for back-to-back accesses to the same row (row hit). Close-page precharges immediately after access. Most controllers use adaptive policies.
CONTROLLER -> PHY -> DRAM
AXI request --> [scheduler] --> READ/WRITE cmd --> [PHY] --> DQ/DQS pins
| |
bank state machine training/margin
refresh counter eye diagramThe PHY implements the electrical interface and training used to capture and launch data reliably. For DDR3/DDR4, write levelling adjusts write DQS relative to CK at the DRAM. Read capture and DQ-to-DQS deskew/centring establish different timing relationships. The available calibration, voltage-reference training and tracking steps depend on the selected memory and PHY.
PHY and controller communicate through a defined interface (DFI is common). A command the controller thinks it issued may fail at the PHY if timing margins are insufficient.
DFI interface: controller sends commands, PHY reports readiness and training status.
Multi-rank systems add chip-select and rank-switching overhead.
ECC placement is implementation-specific: establish whether checking and correction sit in a controller, PHY-integrated block, memory device or another datapath stage before interpreting counters.
DFI interface: controller sends commands, PHY reports readiness and training status.
Multi-rank systems add chip-select and rank-switching overhead.
ECC placement is implementation-specific: establish whether checking and correction sit in a controller, PHY-integrated block, memory device or another datapath stage before interpreting counters.