Place controller near PHY physically — long routes between them add latency and timing risk. Address mapping (which AXI address maps to which rank/bank/row) affects performance as much as scheduler policy.
Multiple ports into one controller need arbitration. CPU, GPU, and display DMA competing for the same DRAM channel need QoS in the controller.
Interleave policy across channels — sequential addresses should stripe.
ECC scrub interacts with refresh — both steal bandwidth.
Low-power modes (self-refresh) need firmware sequencing with controller.