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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals25
  • AMBA Family (APB / AHB / AXI)17
  • Coherence Fabrics (ACE / CHI)17
  • Memory Interfaces (DDR / LPDDR / HBM)17
    • DDR Controller / PHY Split
      • DDR Controller / PHY Split: Concepts
      • DDR Controller / PHY Split: Integration
      • DDR Controller / PHY Split: Debug
      • DDR Controller / PHY Split: Interview
    • Training & Timing Modes
    • Refresh & Bandwidth Efficiency
    • Memory Interface Debug
    • Memory Interfaces (DDR / LPDDR / HBM): Tricky Q&A
  • PCIe & CXL17
  • Embedded Peripherals (I2C / SPI / UART)17
  • High-Speed I/O (USB / Ethernet / MIPI)17
  • Protocol Verification & Compliance17
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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←DDR Controller / PHY Split
  1. Topics
  2. Bus Protocols
  3. Memory Interfaces (DDR / LPDDR / HBM)
  4. DDR Controller / PHY Split
  5. DDR Controller / PHY Split: Debug
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    Interface ProtocolsAll levels

    DDR Controller / PHY Split: Debug

    Debug for DDR Controller / PHY Split.

    Primary debug scenario

    Symptom: Intermittent read timeouts. Training passes. Directed memory tests pass. Mixed workload fails.

    Triage steps

    1. Check whether timeouts correlate with refresh commands and rank availability; correlation narrows the timing window but does not by itself prove an illegal controller command.

    2. Compare training margins at fail temperature vs pass temperature.

    3. Profile bank state and command timing; a high conflict rate can add service work but does not by itself prove the scheduler is unable to keep up.

    4. Check DFI interface: is PHY reporting ready when controller sends commands?

    5. Capture failing read's bank/row/col — is it always the same bank?

    Common pitfalls

    • Assigning the fault to the PHY before checking the controller command trace and the selected device's timing constraints.

    • Assuming boot-time training guarantees margin at every operating corner; check the selected PHY's tracking and recalibration requirements.

    • Ignoring address interleave when profiling bank conflicts.

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    See also

    • DDR Controller / PHY Split: Concepts