Symptom: At 800 MHz, a team widened a 64-bit interface to 128 bits. Throughput rose about 7.1% (4.2 → 4.5 GB/s). The 7 GB/s target exceeds the original 6.4 GB/s ceiling but is below the new 12.8 GB/s ceiling.
Leading hypotheses: The widened path is underutilised. Request admission, return-data supply, consumer backpressure and competing traffic are candidates; bandwidth alone does not choose among them. The original width still imposed a ceiling below the target.
Stall breakdown: AR%, AW%, W%, R%, B% stall fractions.
Correlate request stalls with outstanding occupancy and completion events; a stall percentage alone does not identify the cause.
Check actual burst length on wire — fragmented bursts waste upgrade.
Outstanding depth: master config vs slave acceptance capability.
DRAM: row hit rate, refresh stall%, port arbitration fairness.
Measure useful accepted bytes over the same elapsed interval; separate idle gaps from data-channel backpressure.
Change one suspected limit at a time and compare the same replay against both bandwidth and latency targets.
Quoting peak GB/s without workload.
Width upgrade without stall profile.
Ignoring firmware QoS.
Average BW only — missing latency tail.
Symptom: Benchmark shows 90% of peak DRAM bandwidth in lab. Customer workload gets 40% in field.
Compare access patterns: lab sequential vs customer random/strided.
Row hit rate in field — likely much lower than lab.
Check coherency traffic in SMP customer workload.
Thermal throttling reducing DRAM refresh or clock?
Signing off on synthetic benchmark not representative of customer traffic.