List every master: peak GB/s demand, duty cycle, burst characteristics, latency sensitivity. Sum peak demands — if total exceeds any shared bottleneck (DRAM, NoC, PCIe), you need QoS arbitration, not just wider buses.
Phase-aware budgeting: boot, idle, video playback, gaming, and ML inference have different traffic mixes. Size for the worst phase, verify all phases.
Row per master: name, width, clock, peak GB/s, typical duty, QoS class.
Row per bottleneck: DRAM channels, NoC links, PCIe x4 Gen4, etc.
Sweep offered load per phase and flag the point where a bandwidth or latency requirement first fails.
Reserve headroom justified by measured burstiness, coherency traffic, software variation and operating-corner uncertainty; record the assumptions rather than using a universal percentage.
Attach spreadsheet to architecture signoff.
QoS classes: typically 3-8 levels from critical (CPU icache miss) to bulk (background download). Memory controller maps AXI AxQoS or internal port ID to priority. Misconfigured QoS starves critical paths while bulk traffic shows healthy bandwidth.
Firmware QoS registers are part of the performance contract — document and test them.
CPU instruction fetch starvation: visible as IPC collapse.
Display underrun: visible as frame tears — real-time deadline miss.
PCIe TC (traffic class) maps to VC and service priority.