Illustrative path: a 128-bit AXI data channel at 1 GHz has a 16 GB/s peak. If full-width read beats are accepted on 80% of measured cycles, observed bandwidth is 12.8 GB/s. Two independent 64-bit DDR4-3200 channels have a combined 51.2 GB/s headline; an assumed 70% useful efficiency gives 35.84 GB/s available to this workload only if no competing traffic consumes it. The AXI channel has the lower peak capacity. Its 12.8 GB/s observation is not proof that widening it will help: inspect why the other 20% of cycles carry no accepted data.
If this master instead measures 8 GB/s, the full-width accepted-beat fraction is 50%. Inspect request acceptance, outstanding occupancy, read-data gaps, return backpressure and competing traffic. DRAM locality and burst fragmentation are hypotheses to measure, not conclusions established by a bandwidth number alone.
AXI MASTER BW CHECKLIST
observed bytes/s = accepted useful bytes / elapsed seconds
full-width reads = (width_bits / 8) x clock_hz
x accepted_R_beats / measured_cycles
Path ceiling: minimum of applicable stage capacities,
using the same direction, workload and byte definition.
Investigate stalls to explain the measurement;
do not multiply correlated stall fractions as independent losses.Little's Law relates average work in flight, completed work per second and average time in the same system boundary during steady operation: L = lambda × W. At 10 GB/s and 100 ns, 1,000 bytes are in flight on average. With fixed 64-byte requests, lambda = 10e9 / 64 requests/s, so L = 15.625 requests. At least 16 request slots are therefore necessary to sustain that rate under this simplified model; burstiness, latency variation and admission limits can require more. This average is not a worst-case FIFO-depth guarantee.
At the same byte rate and 200 ns latency, average work doubles to 2,000 bytes or 31.25 fixed 64-byte requests. With 128-byte requests and 100 ns latency, it is 7.8125 requests, still 1,000 bytes. If measurements disagree, first check units, steady-state interval and whether latency and throughput use the same admission/completion boundaries. These are illustrative calculations; a runnable model remains a separate validation task.
Never quote bandwidth without: traffic generator description, duration, warm-up cycles, counter definitions (bytes vs beats), and whether coherency traffic included. Use PMU counters where available. For simulation, define exactly which cycles count toward bandwidth.
Warm-up: exclude first N transactions (cache cold start).
Counters: beats × bytes_per_beat, not valid toggles.
Silicon: use memory controller port counters, not CPU perf alone.