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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals25
    • Layering & Transaction Model
    • Handshake & Backpressure
      • Handshake & Backpressure: Concepts
      • Handshake & Backpressure: Integration
      • Handshake & Backpressure: Debug
      • Handshake & Backpressure: Interview
      • Handshake & Backpressure: Deep Dive
      • Handshake & Backpressure: Worked Examples
    • Ordering & Outstanding Rules
    • Bandwidth & Latency Budgeting
    • Protocol Fundamentals: Tricky Q&A
  • AMBA Family (APB / AHB / AXI)17
  • Coherence Fabrics (ACE / CHI)17
  • Memory Interfaces (DDR / LPDDR / HBM)17
  • PCIe & CXL17
  • Embedded Peripherals (I2C / SPI / UART)17
  • High-Speed I/O (USB / Ethernet / MIPI)17
  • Protocol Verification & Compliance17
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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←Handshake & Backpressure
  1. Topics
  2. Bus Protocols
  3. Protocol Fundamentals
  4. Handshake & Backpressure
  5. Handshake & Backpressure: Deep Dive
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    Interface ProtocolsAll levels

    Handshake & Backpressure: Deep Dive

    Deep Dive for Handshake & Backpressure.

    Deep dive

    AXI-specific handshake rules

    AXI4 adds channel-specific rules on top of valid/ready. AW and W channels are independent in timing, so W can arrive before AW. W has no ID: write-data bursts follow AW request order without interleaving. R and B must match their pending read/write contexts and ordering rules. A master can offer AR while stalled on R; whether it can keep issuing requests depends on available tracking capacity.

    Diagram
    AXI STALL DIAGNOSIS
    
    AR stalled (arvalid=1, arready=0): slave not accepting new reads
    R stalled  (rvalid=1, rready=0):  master not accepting read data
    AW stalled:                       slave not accepting writes
    W stalled:                        often W channel backpressure (check WREADY)
    B stalled:                        master not accepting write responses

    PREADY stretching (APB) vs valid/ready

    APB uses PREADY to stretch the ACCESS phase — functionally similar to ready=0 but with fixed two-phase semantics. AHB uses HREADY to stall the entire pipeline. Understanding these as backpressure variants helps when debugging legacy buses mixed with AXI.

    Throughput equation

    Measure bandwidth as accepted useful bytes divided by elapsed seconds. For fixed full-width beats, bytes/s = bytes_per_beat × clock_hz × accepted_beats / measured_cycles. If the conditional stall fraction is stalled_VALID_cycles / VALID_cycles, then accepted_cycles / measured_cycles = (VALID_cycles / measured_cycles) × (1 - conditional_stall_fraction). The offered-VALID fraction matters: idle cycles are not included in the conditional stall denominator.

    Illustrative 100-cycle window: VALID is high for 90 cycles; 40 of those stall and 50 accept. At 8 bytes per beat and 1 GHz, 400 bytes transfer in 100 ns: 4 GB/s. The conditional stall fraction is 40/90, not 40/100. Doubling width would double bandwidth only if frequency, accepted-beat fraction and useful-lane utilisation stayed unchanged; it cannot overcome a fixed downstream bytes/s ceiling by itself.

    • Record idle, offered, stalled and accepted cycles over the same interval; handle a zero VALID denominator explicitly.

    • Count useful bytes on accepting edges, including write strobes when relevant.

    • Correlate stalls with occupancy and service events before attributing the limit to width, scheduling or acceptance.

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    See also

    • Handshake & Backpressure: Concepts
    • Handshake & Backpressure: Integration
    • Handshake & Backpressure: Debug