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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals25
    • Layering & Transaction Model
    • Handshake & Backpressure
      • Handshake & Backpressure: Concepts
      • Handshake & Backpressure: Integration
      • Handshake & Backpressure: Debug
      • Handshake & Backpressure: Interview
      • Handshake & Backpressure: Deep Dive
      • Handshake & Backpressure: Worked Examples
    • Ordering & Outstanding Rules
    • Bandwidth & Latency Budgeting
    • Protocol Fundamentals: Tricky Q&A
  • AMBA Family (APB / AHB / AXI)17
  • Coherence Fabrics (ACE / CHI)17
  • Memory Interfaces (DDR / LPDDR / HBM)17
  • PCIe & CXL17
  • Embedded Peripherals (I2C / SPI / UART)17
  • High-Speed I/O (USB / Ethernet / MIPI)17
  • Protocol Verification & Compliance17
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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←Handshake & Backpressure
  1. Topics
  2. Bus Protocols
  3. Protocol Fundamentals
  4. Handshake & Backpressure
  5. Handshake & Backpressure: Worked Examples
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    Interface ProtocolsAll levels

    Handshake & Backpressure: Worked Examples

    Worked Examples for Handshake & Backpressure.

    Worked examples

    READY-gated VALID deadlock in simulation

    Setup: New DMA block hangs after 100 transfers. Waveform: valid and ready both low forever after stall. Block worked in previous revision.

    Analysis

    1. Diff RTL: new engineer connected valid = downstream_ready & internal_valid.

    2. First 100 transfers: consumer always ready — no stall, no bug.

    3. With the next item pending, the consumer lowers READY and changes to a policy that waits to observe VALID before raising READY again.

    4. READY gates VALID low, so the consumer never observes the pending item. Both stay low despite internal_valid=1. If an existing stalled offer was withdrawn, that is an additional handshake violation.

    5. Fix: retain the pending item and assert VALID independently of READY; hold its payload until accepted. Add storage if registered backpressure permits extra input acceptances.

    Outcome: The bug is exposed by a simulation that combines a pending item with a destination waiting for VALID. An always-ready test hides it.

    Lesson: Directed tests without backpressure are insufficient for handshake validation.

    Low utilisation — test outstanding capacity first

    Setup: Illustrative full-width 64-bit AXI read path at 1.25 GHz: theoretical peak 10 GB/s, observed 3.2 GB/s. The team proposes a 128-bit variant before examining request admission.

    Analysis

    1. Count accepted full-width R beats: 32% of measured cycles. Separate cycles with RVALID=0 from those with RVALID=1 and RREADY=0.

    2. In the illustrative trace, RREADY remains high but data arrives in groups separated by gaps. Four requests occupy all of the master's tracking slots; request issuance pauses until a completion frees a slot.

    3. Assume the controller and all intermediate trackers can support 16 requests. A controlled replay increasing the master limit from four to 16 measures 7.8 GB/s at the same width and clock, below the 10 GB/s ceiling.

    4. The improvement supports the limited-concurrency hypothesis for this replay. It does not establish that wider data could never help, or predict performance for another traffic pattern.

    Outcome: The replay improved from 32% to 78% of its data-channel peak after changing request capacity alone. No unmeasured gain for a width change is claimed.

    Lesson: Measure which channel stalls and why before any width/frequency change.

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    See also

    • Handshake & Backpressure: Concepts
    • Handshake & Backpressure: Integration
    • Handshake & Backpressure: Debug