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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals25
    • Layering & Transaction Model
    • Handshake & Backpressure
      • Handshake & Backpressure: Concepts
      • Handshake & Backpressure: Integration
      • Handshake & Backpressure: Debug
      • Handshake & Backpressure: Interview
      • Handshake & Backpressure: Deep Dive
      • Handshake & Backpressure: Worked Examples
    • Ordering & Outstanding Rules
    • Bandwidth & Latency Budgeting
    • Protocol Fundamentals: Tricky Q&A
  • AMBA Family (APB / AHB / AXI)17
  • Coherence Fabrics (ACE / CHI)17
  • Memory Interfaces (DDR / LPDDR / HBM)17
  • PCIe & CXL17
  • Embedded Peripherals (I2C / SPI / UART)17
  • High-Speed I/O (USB / Ethernet / MIPI)17
  • Protocol Verification & Compliance17
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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←Handshake & Backpressure
  1. Topics
  2. Bus Protocols
  3. Protocol Fundamentals
  4. Handshake & Backpressure
  5. Handshake & Backpressure: Integration
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    Interface ProtocolsAll levels

    Handshake & Backpressure: Integration

    Integration for Handshake & Backpressure.

    Integration in practice

    FIFO sizing and clock domains

    Define Q(t) = Q(0) + accepted_writes(t) - completed_reads(t). Required storage covers the largest Q over the allowed traffic and backpressure scenarios. Clock rates, relative phase, burst timing, consumer pauses and stop latency determine those event counts; a frequency ratio alone does not determine depth. If arrival rate remains above guaranteed service forever and the producer cannot be stopped, no finite FIFO is sufficient.

    Illustrative synchronous event budget: start empty, accept one item at each of edges 1–8, and complete reads only at edges 4 and 8. The peak post-edge occupancy is six items. If instead you assert a stop request at occupancy six and two further items can be accepted with no guaranteed reads before the stop takes effect, storage must cover eight items. These are explicit traffic assumptions, not a universal depth recommendation.

    For a conventional asynchronous FIFO, synchronised Gray-coded pointer information can make the local view conservative and delay recognition of freed space or new data. Account for that latency in the throughput and stop/restart budget; two synchroniser stages do not automatically mean two extra data slots. Use the selected FIFO implementation's documented flag, reset and physical CDC constraints. Do not synchronise a multi-bit data bus with independent bit synchronisers.

    • Almost-full threshold: reserve enough free slots for the maximum additional accepted items after requesting a stop.

    • Almost-empty threshold: cover refill/wakeup latency and required consumer service, rather than choosing an arbitrary percentage.

    • Synchronous FIFOs: simpler, but still size for burst not average.

    Arbiters and shared slaves

    When multiple masters share one slave port, the arbiter muxes valid/ready streams. A master can be stalled even when the slave is ready — the arbiter granted another master. QoS and priority prevent starvation of critical paths.

    Round-robin arbiters are fair but add latency variance. Fixed-priority is predictable but can starve low-priority masters indefinitely. Weighted fair queuing is common in NoCs and memory controllers.

    1. Document arbiter policy for each shared slave.

    2. Measure per-master stall rate — identify starvation.

    3. QoS tie-break: CPU > GPU display > bulk DMA is typical.

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    See also

    • Handshake & Backpressure: Interview
    • Handshake & Backpressure: Deep Dive
    • Handshake & Backpressure: Worked Examples