Allocate ID width for independent ordering streams and queue capacity for outstanding transactions separately. One ID can carry four or more outstanding reads if an ordered per-ID context FIFO tracks them; RID selects the stream, its head selects the transaction. A 2-bit downstream ID port permits four ID values, not necessarily only four outstanding transactions. A bridge may serialize, stall, or queue multiple contexts per mapped ID while preserving upstream order and response association. A design choosing one live context per ID does have a four-context limit, but that is its implementation policy.
Per master: max outstanding reads, max outstanding writes.
ID width: enough for independent ordering streams; ceil(log2(max OSTD)) applies only when every live transaction requires a unique ID.
Per bridge: remap table, per-ID ordered queues, total context capacity, and legal backpressure on exhaustion. Never reuse a mapping while untracked responses remain.
System: document admission/backpressure when requested concurrency exceeds downstream acceptance; not every upstream slot needs a simultaneously available slave slot.
Deliver a programming guide: which memory regions are strongly ordered, which allow relaxed reorder, where fences are required between CPU and device. Hardware teams often omit this; software discovers bugs in production.
Device MMIO: typically strongly ordered — document if not.
DMA coherent buffers: hardware coherency ≠ write ordering to doorbell.
Shared queues: producer/consumer indices need barrier between data and flag.