Setup: Illustrative DMA reads ordinary memory through a width converter. The converter chooses to split one aligned 16-byte parent read into two eight-byte single-beat downstream reads using distinct IDs. Multi-ID stress reveals swapped halves; the example excludes device-register side effects.
Parent ID=5 reads bytes 0x1000–0x100F. Child ID=1 reads 0x1000–0x1007; child ID=2 reads 0x1008–0x100F.
Distinct downstream IDs allow child 2 to complete before child 1. Two children on the same ID could not be assumed to reorder this way.
A faulty converter appends child data in completion order instead of placing it at the recorded parent offset.
Retain parent context, child identity and byte offset. Fill the high half from child 2, the low half from child 1, then present the correctly assembled parent response.
Check both child completion permutations and a failed child; upstream status and acceptance must follow the defined conversion contract.
Outcome: Bridge width converter reorder bug. Fix: response reorder buffer in converter.
Lesson: Multi-ID stress exposes bridge bugs that single-ID directed tests miss.
Setup: Driver writes DMA_SRC, DMA_DST, DMA_LEN, then DMA_START. Occasionally DMA uses previous transfer's addresses.
Capture the actual MMIO access sequence and accepted transactions at the DMA registers; a store-buffer guess is not evidence of reordering.
Check register mapping, accessor semantics, reset and ownership before deciding which ordering guarantee is missing.
If the register target sees DMA_SRC before DMA_START with correct values, investigate target latching, programming rules and completion handling instead of adding an arbitrary barrier.
If the platform contract requires publication ordering that the driver omitted, repair it using the documented accessors/synchronisation and repeat the failing case. This example does not prescribe a universal DMB or ACE transaction.
Outcome: Use the observed register order and platform contract to distinguish driver publication from target behaviour; the symptom alone does not decide fault ownership.
Lesson: Transaction layer includes software-visible order, not just bus order.