The clock period minus fixed costs leaves the budget for logic and wire. Dividing by a typical gate delay gives a depth budget for writing RTL.
Item | Example |
|---|---|
Clock period | 2.0 ns (500 MHz) |
Clock-to-Q + setup | 0.35 + 0.12 = 0.47 ns |
Uncertainty and skew margin | 0.15 ns |
Left for logic and wire | 2.0 − 0.47 − 0.15 = 1.38 ns |
Typical gate + wire delay | 0.10 ns (illustrative) |
Depth budget | ≈ 13 levels |
Read the bar from left to right: one clock period from the launch edge to the capture edge.
The fixed costs (clock-to-Q, setup and margin) take 0.62 ns before any logic is placed.
The highlighted segment is all the logic and wire gets: 1.38 ns.
Thirteen 0.10 ns levels fit inside it; a fourteenth would need 1.40 ns and fail.
The second table compares earlier mapping examples with the illustrative 13-level estimate. Gate levels are not equal delays: calibrate against the target library, synthesis flow, corner, load, slew and wire estimates before choosing an architecture. These counts are not measured timing for your target.
Operation (earlier measurement) | Levels | Fits 13? |
|---|---|---|
8-bit adder | 15 | Above estimate; inspect mapped delay before choosing a fix |
32-bit comparator | 20 | No: restructure or pipeline |
16-bit adder | 31 | No: prefix adder or two stages |
8×8 multiplier | 30 | No: multi-cycle or pipeline |
Seven rules help allocate the budget; registered boundaries still require setup/hold, input/output delays, slew/load and clock relationship constraints.
Budget and register the interfaces where appropriate. Registers isolate internal logic from boundary paths; they do not remove pin-to-register or register-to-pin timing budgets, and extra ranks change consumer latency.
Know your longest paths from the architecture, before synthesis: wide add, multiply, compare, priority, mux trees.
Avoid long chains of dependent operators in one expression (a + b + c + d as a chain; wide if/else if ladders).
Put late-arriving signals last in a logic expression: a late select drives the final mux, not the first.
Limit fanout: a control signal that goes to hundreds of flops needs a duplicated driver.
Make the number of pipeline stages a parameter when the path is uncertain.
Don't share a slow resource across critical paths in a way that adds muxes in front.
1.25 − 0.45 − 0.10 = 0.70 ns, so about 7 levels.
The 0.10 ns gate-plus-wire delay and the 13-level budget are teaching numbers. The level counts come from earlier mapping examples and are not measured timing for your target.