Address map

The table of every region the chip answers to: base, size, access, cacheability and security attribute. One table feeds the decoder, the software headers and the tests.

What an Address Map Is

Alias

Two or more addresses that reach the same register or memory location. In NanoSoC the DMA decodes only 8 address bits behind a 4 KB slot, so its 256-byte window repeats 16 times.

Holes, Aliases and Reserved Space

Alignment

A region's base is a multiple of its size, which for a power-of-two size means the low address bits below the size are zero. It lets the decoder compare only the upper bits.

Sizes, Alignment and Power-of-Two Windows

Decode

Comparing address bits with a region's base to produce a select for one slave. NanoSoC decodes the ROM, two SRAMs and the APB window at the interconnect.

Decode from Address Bits

Decode error (DECERR)

The AXI response, code 2'b11, returned when an address reaches no slave. In NanoSoC the default slave at the interconnect produces it.

DECERR Versus SLVERR Versus PSLVERR

Default slave

A slave that answers every address no other slave claims, with an error response and no side effect, so the master never waits for a reply that cannot come.

Default-Slave Design

Generated header

A software header, register document or test table produced from the same machine-readable map description as the hardware, so they cannot drift apart.

Generated Headers and the Map Document

Hole

An address range with no slave. Accesses are answered by a default slave: NanoSoC holes H1, H2 and H4 return DECERR, and H3 (reserved APB slots 7 to 15) returns SLVERR.

Holes, Aliases and Reserved Space

IP-XACT

A public standard XML format that describes a block's ports, registers and bus interfaces and a design's connections, used to generate the top level and its documents.

What IP-XACT Describes

PSLVERR

The APB slave error signal, meaningful in the last cycle of an access. The bridge turns it into AXI SLVERR. The NanoSoC DMA raises it for any offset it does not map.

DECERR Versus SLVERR Versus PSLVERR

Register block

The set of registers behind one slot, with offsets, fields, access types and reset values. The specification must say what writes to read-only fields and unmapped offsets do.

Designing a Register Block

Slave error (SLVERR)

The AXI response, code 2'b10, for an access that reached a slave which refused or failed it. NanoSoC returns it for a non-secure access to SRAM1 and for the APB holes.

DECERR Versus SLVERR Versus PSLVERR

Slot decode

A second decode inside a window: after the interconnect selects the APB window, NanoSoC uses address bits [15:12] to pick one of seven 4 KB slots.

Hierarchical Decode and Slot Decode

W1C (write one to clear)

A register bit access type: writing 1 clears the bit, writing 0 does nothing. NanoSoC status flags such as DMA DONE and ERR use it.

Checking the Register Specification

Window

The address range a slave claims. A window can be larger than the slave behind it, which is how aliases and mirrors appear.

Sizes, Alignment and Power-of-Two Windows